EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 972

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–14
Figure 1–4. MegaWizard Plug-In Manager—ALTGX (PLL/Ports Screen)
Table 1–2. MegaWizard Plug-In Manager Options (PLL/Ports Screen) (Part 1 of 3)
Stratix IV Device Handbook Volume 3
Train receiver clock and data
recovery (CDR) from
pll_inclk.
Use ATX Transmitter PLL
ALTGX Setting
PLL/Ports Screen for the Parameter Settings
Figure 1–4
for the Parameter Settings.
Table 1–2
Plug-In Manager for your ALTGX custom megafunction variation.
If you select this option, the input reference clock to
the CMU PLL trains the receiver CDR.
This option is only available for certain data rates.
Refer to the DC and Switching Characteristics for
Stratix IV Devices chapter for the supported data
rates.
This option enables the auxiliary transmitter PLL.
This is a low-jitter PLL that resides between the
transceiver blocks and can be used as a transmitter
PLL.
lists the available options on the PLL/ports screen of the MegaWizard
shows the PLL/Ports screen of the ALTGX MegaWizard Plug-In Manager
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Table 1-77 in the
Architecture in Stratix IV Devices
chapter.
“Auxiliary Transmit (ATX) PLL Block”
section in the
in Stratix IV
Clocking in Stratix IV Devices
and the
Characteristics for Stratix IV Devices
section.
DC and Switching
February 2011 Altera Corporation
Devices, the
Reference
Transceiver Architecture
Transceiver
Parameter Settings
Transceiver
chapter,