EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 904

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–58
Figure 5–29. Correct Input Reference Clock Connections When Reusing a .mif
Note to
(1) The red lines represent the alternate source of REFCLK.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
5–29:
1
156.25 MHz
125 MHz
Figure 5–29
You can re-use the .mif generated for a transceiver channel on one side of the device
for a transceiver channel on the other side of the device, only if the input reference
clock frequencies and order of the pll_inclk_rx_cruclk[] ports in the ALTGX
instances on both sides are identical.
In addition to the input reference clock requirements when re-using a .mif, refer to
“Guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en Ports” on page 5–58
additional ways to re-use a .mif.
Guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en Ports
This section describes when to enable the logical_tx_pll_sel and
logical_tx_pll_sel_en ports and how to use them in the following dynamic
reconfiguration modes:
■
■
■
These are optional input ports to the ALTGX_RECONFIG instance.
Channel and CMU PLL reconfiguration mode
Channel reconfiguration with transmitter PLL select mode
CMU PLL reconfiguration mode
shows the correct input reference clock connections when re-using a .mif.
(1)
(1)
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
Stratix IV GX Device
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Transceiver Block 0
Transceiver Block 1
Instance 2
Instance 1
ALTGX
February 2011 Altera Corporation
ALTGX
for