EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 139
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Figure 5–19. Stratix IV PLL Block Diagram
Notes to
(1) The number of post-scale counters is seven for left and right PLLs and ten for top and bottom PLLs.
(2) This is the VCO post-scale counter K.
(3) The FBOUT port is fed by the M counter in Stratix IV PLLs.
February 2011 Altera Corporation
from adjacent PLL
Cascade input
GCLK/RCLK
clock inputs
Dedicated
pfdena
Figure
5–19:
1
4
Figure 5–19
Stratix IV PLL.
You can drive the GCLK or RCLK inputs using an output from another PLL, a
pin-driven GCLK or RCLK, or through a clock control block provided the clock
control block is fed by an output from another PLL or a pin-driven dedicated GCLK
or RCLK. An internally generated global signal or general purpose I/O pin cannot
drive the PLL.
PLL Clock I/O Pins
Each top and bottom PLL supports six clock I/O pins, organized as three pairs of
pins:
■
■
■
inclk0
inclk1
1st pair—two single-ended I/O or one differential I/O
2nd pair—two single-ended I/O or one differential external feedback input
(FBp/FBn)
3rd pair—two single-ended I/O or one differential input
Switchover
Clock
Block
shows a simplified block diagram of the major components of the
÷n
clkswitch
clkbad0
clkbad1
activeclock
PFD
Circuit
Lock
CP
locked
LF
VCO
8
no compensation mode
ZDB, External feedback modes
LVDS Compensation mode
Source Synchronous, normal modes
÷2
(2)
To DPA block on
Left/Right PLLs
/2, /4
8
8
Stratix IV Device Handbook Volume 1
÷C0
÷C1
÷C2
÷C3
÷Cn
÷m
(1)
Casade output
to adjacent PLL
FBIN
DIFFIOCLK network
GCLK/RCLK network
GCLKs
RCLKs
External clock
outputs
DIFFIOCLK from
Left/Right PLLs
LOAD_EN from
Left/Right PLLs
FBOUT (3)
External
memory
interface DLL
5–23
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