EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 604

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–160
Figure 1–126. IEEE 802.3ae PCS Synchronization State Diagram
Note to
(1) This figure is from IEEE P802.3ae.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
1–126:
Word Aligner
The word aligner in XAUI functional mode is configured in automatic
synchronization state machine mode. The Quartus II software automatically
configures the synchronization state machine to indicate synchronization when the
receiver receives four /K28.5/ comma code groups without intermediate invalid code
groups. The synchronization state machine implemented in XAUI mode is compliant
to the PCS synchronization state diagram specified in Clause 48 of the IEEE P802.3ae
specification and is shown in
2
3
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
SYNC_ACQUIRED_2
SYNC_ACQUIRED_3
SYNC_ACQUIRED_4
cgbad
cgbad
cgbad
[PUDI * signal_detect=FAIL +
mr_loopback=FALSE] +
PUDI(![/COMMA/])
⇐
⇐
⇐
⇐
⇐
⇐
! rx_even
! rx_even
! rx_even
0
0
0
PUDI(![/|DV|/]
cgbad
PUDI(![/|DV|/]
cgbad
PUDI(![/|DV|/]
cggood
cggood
cggood
Figure
SUDI
SUDI
SUDI
SUDI
SUDI
SUDI
rx_even
rx_even
COMMA_DETECT_1
rx_even
COMMA_DETECT_2
COMMA_DETECT_3
sync_status
ACQUIRE_SYNC_1
ACQUIRE_SYNC_2
LOSS_OF_SYNC
rx_even
rx_even
rx_even
cgbad
cgbad
cgbad
cgbad
⇐
⇐
⇐
⇐
⇐
⇐
! rx_even
! rx_even
! rx_even
PUDI([/|DV|/]
rx_even=FALSE+PUDI([/COMMA/]
PUDI([/|DV|/]
rx_even=FALSE+PUDI([/COMMA/]
(signal_detect=OK+mr_loopback=TRUE)* *
PUDI([/COMMA/]
1–126.
TRUE
TRUE
TRUE
⇐
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
SYNC_ACQUIRED_2A
SYNC_ACQUIRED_3A
SYNC_ACQUIRED_4A
(Note 1)
FAIL
PUDI([/|DV|/]
power_on=TRUE+mr_main_rest=TRUE +
(signal_detectCHANGE=TRUE +
mr_loopback=FALSE +PUDI)
⇐
⇐
⇐
⇐
⇐
⇐
! rx_even
! rx_even
! rx_even
2
3
good_cgs + 1
good_cgs + 1
good_cgs + 1
Chapter 1: Transceiver Architecture in Stratix IV Devices
cggood
cggood
PUDI(![/COMMA/]
*∉[/INVALID/]
PUDI(![/COMMA/]
*∉[/INVALID/]
SUDI
SYNC_ACQUIRED_1
*good_cgs = 3
*good_cgs = 3
rx_even
sync_status
⇐
cggood
cggood
cggood
! rx_even
⇐
cggood
OK
*good_cgs = 3
*good_cgs = 3
*good_cgs = 3
*good_cgs = 3
cggood
February 2011 Altera Corporation
Transceiver Block Architecture