EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 1040
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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2–22
Figure 2–5. FC4G Instance Settings (PLL/Ports Screen)
Stratix IV Device Handbook Volume 3
f
■
For more information about receiver CDR and lock modes, refer to the “Receiver
Channel Datapath” section of
PLL/Ports screen—Check the Train Receiver CDR from PLL inclk option, as
shown in
used for the CMU PLL is provided as a training clock to the receiver CDR.
■
■
■
Check the pll_powerdown signal. This signal allows you to power down the
CMU PLL. Use this signal as part of your reset sequence.
Check the pll_locked signal. This signal indicates whether the CMU PLL is
locked to the input reference clock. The user logic waits until the pll_locked
signal goes high before transmitting data.
Check the rx_freqlocked signal. This signal indicates whether the receiver
CDR is locked to data. When the receiver CDR is configured in automatic lock
mode, assert the rx_digitalreset signal if the rx_freqlocked signal goes low
to keep the receiver PCS under reset. Altera recommends specific transceiver
reset sequences to ensure proper device operation.
Figure
2–5. When you select this option, the same input reference clock
Transceiver Architecture in Stratix IV Devices
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
February 2011 Altera Corporation
chapter.
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