EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 901

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–27. CMU PLL Reconfiguration .mif Write Transaction
February 2011 Altera Corporation
reconfig_address_out[5:0]
reconfig_mode_sel[2:0]
channel_reconfig_done
reconfig_address_en
reconfig_data[15:0]
f
reconfig_clk
write_all
ALTGX_RECONFIG Plug-In Manager Setup for CMU PLL Reconfiguration Mode
For more information, refer to
Setup for Channel and CMU PLL Reconfiguration Mode” on page
CMU PLL Reconfiguration Operation
Set the reconfig_mode_sel[2:0] signal to 3’ b100 to activate this mode.
Figure 5–27
dynamic reconfiguration controller asserts the channel_reconfig_done signal to
indicate that the CMU PLL reconfiguration is complete. In this example, the
transceiver channel is configured in Receiver and Transmitter configuration.
Therefore, the .mif size is 8.
You can optionally choose to trigger write_all once by selecting the continuous write
operation in the ALTGX_RECONFIG MegaWizard Plug-In Manager. The Quartus II
software then continuously writes all the words required for reconfiguration.
For guidelines regarding re-using .mifs, specifying input reference clocks, or using
logical_tx_pll_sel ports, refer to
For more information about reset, refer to the “Reset Sequence when Using Dynamic
Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the
Reset Control and Power Down in Stratix IV Devices
busy
1st 16 bits
shows a .mif write transaction in CMU PLL reconfiguration mode. The
Addr0
Don’t care
2nd 16 bits
“ALTGX_RECONFIG MegaWizard Plug-In Manager
Addr1
3’b100
“Special Guidelines” on page
Stratix IV Device Handbook Volume 2: Transceivers
chapter.
8th 16 bits Don’t care
Addr7
5–56.
5–46.
Addr0
5–55