EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 623
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–145. SDI Mode
Note to
(1) Not supported in Stratix IV GT devices.
February 2011 Altera Corporation
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
PMA-PCS Interface
Interface Frequency
Fabric-Transceiver
Functional Modes
Low-Latency PCS
Encoder/Decoder
Fabric-Transceiver
Rate Match FIFO
Data Rate (Gbps)
(Pattern Length)
Channel Bonding
Functional Mode
TX PCS Latency
Interface Frequency
RX PCS Latency
Figure
Byte Ordering
Interface Width
Word Aligner
Byte SerDes
8B/10B
FPGA
FPGA
(MHz)
Width
1–45:
Figure 1–145
devices.
8-bit
Single
Width
10-bit
Basic
shows SDI mode configurations supported in Stratix IV GX and GT
Disabled
Disabled
148.35
16-bit
10-Bit
148.5/
9 - 11
5 - 6
(1.485/1.4835) (1)
Double
Width
Disabled
Stratix IV GX and GT Configurations
Disabled
HD-SDI
Disabled
Bit-Slip
20-bit
x1
Disabled
Enabled
74.175
74.25/
20-Bit
4 - 5.5
6 - 8
10-bit
PIPE
10-bit
XAUI
SDI
GIGE
10-bit
Protocol
SRIO
10-bit
Stratix IV Device Handbook Volume 2: Transceivers
SONET
/SDH
8-bit
16-bit
(OIF)
CEI
(2.97/2.967)
Disabled
Disabled
Disabled
Disabled
Enabled
148.5/
148.35
3G-SDI
Bit-Slip
20-bit
4 - 5.5
x1
6 - 8
10-bit
SDI
10-Bit
Deterministic
Latency
20-Bit
1–179
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