EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 703

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Figure 2–17. Transmitter Datapath Clocking in x8 Bonded Configuration
Note to
(1) The red lines represent the FPGA fabric-Transceiver interface clock, the green lines represent the low-speed parallel clock, and the blue lines
February 2011 Altera Corporation
represent the high-speed serial clock.
Figure
tx_coreclk[7:4]
tx_coreclk[3:0]
FPGA
Fabric
2–17:
1
FPGA Fabric-Transceiver
FPGA Fabric-Transceiver
coreclkout
hard IP
hard IP
PCIe
Interface Clock
PCIe
Interface Clock
Figure 2–17
configurations when clocked using the CMU channel in the master transceiver block.
Figure 2–18
locations and PCIe logical lane to physical transceiver channel mapping in all
Stratix IV devices.
The Quartus II compilation errors out if you do not map the PCIe logical lanes to the
physical transceiver channels, as shown in
Interface
Interface
PIPE
PIPE
Reference
Reference
Clock
Clock
Input
Input
through
shows the transmitter datapath clocking in PCIe ×8 channel bonding
/2
Figure 2–20
CMU1 PLL
CMU0 PLL
CMU1 PLL
CMU0 PLL
Compensation
Compensation
wrclk
wrclk
TX Phase
TX Phase
FIFO
FIFO
rdclk
rdclk
show the allowed master and slave transceiver block
Slave Transceiver Block
wrclk
wrclk
CMU0 Clock
CMU1 Clock
CMU1 Clock
Master Transceiver Block
CMU0 Clock
Serializer
Serializer
Divider
Divider
Divider
Divider
Byte
Byte
/2
/2
CMU1 Channel
CMU0 Channel
rdclk
rdclk
CMU0 Channel
CMU1 Channel
Transmitter Channel PCS
Figure 2–18
Transmitter Channel PCS
Low-Speed Parallel Clock
from CMU0 of the Master
Low-Speed Parallel Clock
from CMU0 of the Master
(Note 1)
Transceiver Block
Transceiver Block
Low-Speed Parallel Clock
High-Speed Serial Clock
8B/10B
Encoder
8B/10B
Encoder
Stratix IV Device Handbook Volume 2: Transceivers
through
Transmitter Channel PMA
Transmitter Channel PMA
Figure
Serializer
Serializer
2–20.
2–31