EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 749
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 2: Transceiver Clocking in Stratix IV Devices
Configuration Examples
Table 2–19. Quartus II Assignments
February 2011 Altera Corporation
From
To
Assignment Name
Value
Note to
(1) This is an example design hierarchy path for the tx_clkout[4] signal.
Table
Configuration Example 3: Configuring Sixteen Channels Across Four
Transceiver Blocks
2–19:
1
Table 2–19
scheme shown in
This example relates to
Clock” on page
Figure 2–40
transceiver blocks. The incoming serial data to all 16 channels has a 0 PPM frequency
difference with respect to each other. The rx_coreclk ports of all 16 channels are
connected together and driven by rx_clkout[9] in transceiver block GXBR2.
rx_clkout[9] also clocks the receiver data and status signals of all 16 channels in the
FPGA fabric. With this clocking scheme, only one global, regional, or global and
regional clock resource is used by rx_clkout[9].
top_level/top_xcvr_instance1/altgx_component/tx_clkout[4]
tx_dataout[15..0]
GXB 0 PPM Core Clock Setting
ON
lists the Quartus II assignments that you must make for the clocking
shows 16 non-bonded channels without rate matcher located across four
2–69.
Figure
“User-Selected Receiver Phase Compensation FIFO Read
2–38.
Stratix IV Device Handbook Volume 2: Transceivers
(1)
2–77
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