EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 286

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–8
LVDS SERDES
Figure 8–4. LVDS SERDES
Notes to
(1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, the two left
(2) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(3) The tx_in and rx_out ports have a maximum data width of 10 bits.
Stratix IV Device Handbook Volume 1
tx_coreclock
rx_divfwdclk
rx_outclock
and right PLLs are required.
FPGA
Fabric
rx_out
tx_in
Figure
8–4:
10
10
Figure 8–4
circuitry in the left and right banks. This diagram shows the interface signals of the
transmitter and receiver data path. For more information, refer to
Transmitter” on page 8–11
3
(LOAD_EN, diffioclk)
IOE Supports SDR, DDR, or
2
(Note
(LVDS_LOAD_EN, diffioclk,
DIN DOUT
Non-Registered Datapath
Deserializer
DOUT
Serializer
1), (2),
tx_coreclock)
DIN
shows a transmitter and receiver block diagram for the LVDS SERDES
IOE
2
Left/Right PLL
2
(3)
3
DOUT
Clock MUX
(LVDS_LOAD_EN,
Bit Slip
LVDS_diffioclk,
IOE
rx_outclock
diffioclk
DIN
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
and
rx_inclock/tx_inclock
“Differential Receiver” on page
LVDS Transmitter
LVDS Receiver
DOUT
Synchronizer
IOE Supports SDR, DDR, or
Non-Registered Datapath
DIN
8 Serial LVDS
Clock Phases
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
Retimed
DPA Clock
Data
DPA Circuitry
February 2011 Altera Corporation
DIN
8–17.
“Differential
+
-
LVDS Clock Domain
DPA Clock Domain
+
-
LVDS SERDES
rx_in
tx_out