EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 898
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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5–52
Stratix IV Device Handbook Volume 2: Transceivers
The PLL logical reference index of additional PLLs outside the transceiver block can
only be 2 or 3.
■
■
For more information about the PLL logical reference index of CMU PLLs within the
same transceiver block, refer to
PLL” on page
ALTGX_RECONFIG MegaWizard Plug-In Manager Setup for Channel Reconfiguration with
Transmitter PLL Select Mode
For more information, refer to the
Manager Setup for Channel and CMU PLL Reconfiguration Mode” on page
Channel Reconfiguration with Transmitter PLL Select Operation
Read transactions are not allowed in this mode.
Figure 5–25
transceiver channel. The .mif write transaction in channel reconfiguration with
transmitter PLL select mode remains the same except for the
reconfig_mode_sel[2:0] value and the difference in the number of .mif words used.
In this example, the transceiver channel is configured in Receiver and Transmitter
configuration. Therefore, the .mif size is 8.
You can optionally choose to trigger write_all once by selecting the continuous write
operation in the ALTGX_RECONFIG MegaWizard Plug-In Manager. The Quartus II
software then continuously writes all the words required for reconfiguration.
When you enable the Use central clock divider to drive the transmitter channels
using ×4/×N lines option for an additional PLL, you can only select between 2 or 3
as the PLL logical reference index.
When you disable the Use central clock divider to drive the transmitter channels
using ×4/×N lines option for an additional PLL, the additional PLL is one of the
CMU PLLs within the same transceiver block. Therefore, the PLL logical reference
index is either 0 or 1.
Selecting the PLL Logical Reference Index for Additional PLLs
shows a .mif write transaction when dynamically reconfiguring a
5–29.
“Selecting the Logical Reference Index of the CMU
“ALTGX_RECONFIG MegaWizard Plug-In
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
5–46.
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