EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 231

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–6. Number of DQS/DQ Groups per Bank in EP4SGX110 Devices with 16 Transceivers in the 1152-Pin FineLine
BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX110 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
February 2011 Altera Corporation
Groups for a ×36 QDR II+/QDR II SRAM Interface” on page
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Figure
26 User I/Os
I/O Bank 1C
I/O Bank 1A
32 User I/Os
x16/x18=0
x16/x18=1
x8/x9=1
x8/x9=2
DLL0
DLL1
x4=3
7–6:
x4=4
(Note
1), (2), (3), (4),
I/O Bank 8A
40 User I/Os
I/O Bank 3A
40 User I/Os
x16/x18=1
x16/x18=1
UP
x8/x9=3
x8/x9=3
x4=6
x4=6
and R
DN
pins for OCT calibration. If two pins of a ×4 group are used as R
(5)
24 User I/Os
I/O Bank 8C
x16/x18=0
I/O Bank 3C
24 User I/Os
x8/x9=1
x16/x18=0
x4=2
x8/x9=1
in the 1152-Pin FineLine BGA
x4=2
EP4SGX110 Devices
(with 16 Transceivers)
7–26.
UP
24 User I/Os
I/O Bank 7C
x16/x18=0
24 User I/Os
I/O Bank 4C
x16/x18=0
x8/x9=1
and R
x8/x9=1
x4=3
x4=3
DN
pins, but you cannot use a ×4 group for memory interfaces if two pins
I/O Bank 7A
40 User I/Os
I/O Bank 4A
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
x4=6
x4=6
26 User I/Os
I/O Bank 6C
I/O Bank 6A
32 User I/Os
x16/x18=0
x16/x18=1
x8/x9=1
x8/x9=2
UP
x4=3
DLL3
x4=4
DLL2
Stratix IV Device Handbook Volume 1
and R
DN
“Combining ×16/×18 DQS/DQ
pins for OCT calibration, you
7–11