EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 829

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
February 2011 Altera Corporation
PCIe Initialization/Compliance Phase
After the device is powered up, a PCIe-compliant device goes through the compliance
phase during initialization. In this phase, the PCIe protocol requires the system to be
operating at the Gen 1 data rate. The rx_digitalreset signal must be de-asserted
during this compliance phase to achieve transitions on the pipephydonestatus signal,
as expected by the link layer. The rx_digitalreset signal is de-asserted based on the
assertion of the rx_freqlocked signal.
During the initialization/compliance phase, do not use the rx_freqlocked signal to
trigger a de-assertion of the rx_digitalreset signal. Instead, follow these reset steps:
1. After power up, assert pll_powerdown for a minimum period of t
2. When the transmitter PLL locks, as indicated by the pll_locked signal going high
3. When the receiver CDR locks to the input reference clock, as indicated by the
PCIe Normal Phase
For the normal PCIe phase, follow these steps:
1. After completion of the Initialization/Compliance phase, during the normal
2. Wait for the rx_freqlocked signal to go high again. In this phase, the received data
3. After the rx_freqlocked signal goes high, wait for at least 4 μs before asserting
4. During normal operation, after you speed-negotiate to the Gen 2 data rate,
time between markers 1 and 2). Keep the tx_digitalreset, rx_analogreset, and
rx_digitalreset signals asserted during this time period. After you de-assert the
pll_powerdown signal, the transmitter PLL starts locking to the transmitter input
reference clock.
(marker 3), de-assert tx_digitalreset. For a receiver operation, wait for the busy
signal to be de-asserted. rx_analogreset is then de-asserted. After
rx_analogreset is de-asserted, the receiver CDR starts locking to the receiver
input reference clock.
rx_pll_locked signal going high at marker 7 in
rx_digitalreset signal (marker 8). After de-asserting rx_digitalreset, the
pipephydonestatus signal transitions from the transceiver channel to indicate the
status to the link layer. Depending on its status, pipephydonestatus helps with the
continuation of the compliance phase. After successful completion of this phase,
the device enters into the normal operation phase.
operation phase at the Gen 1 data rate, when the rx_freqlocked signal is
de-asserted (marker 10 in
signifying the lock-to-reference clock.
is valid (not electrical idle) and the receiver CDR locks to the incoming data.
Proceed with the reset sequence after assertion of the rx_freqlocked signal.
rx_digitalreset (marker 12 in
that the receiver phase compensation FIFO is initialized.
asserting the rx_digitalreset signal causes the PCIe rate switch circuitry to
switch the transceiver to the Gen 1 data rate.
Data from the transceiver block is not valid from the time the rx_freqlocked
signal goes low (marker 10 in
de-asserted (marker 13 in
period (between markers 10 and 13 in
Figure
Figure
Figure
Figure
4–12), wait for the rx_pll_locked signal assertion
4–12). The PLD logic ignores the data during this
4–12) to the time rx_digitalreset is
Figure
4–12) for two parallel receive clock cycles so
4–12).
Stratix IV Device Handbook Volume 2: Transceivers
Figure
4–12, de-assert the
pll_powerdown
(the
4–23