EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 543
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–37. Receiver Phase Compensation FIFO Write Clock Source
Table 1–38. Receiver Phase Compensation FIFO Read Clock Source
February 2011 Altera Corporation
Non-bonded channel
configuration with rate matcher
Non-bonded channel
configuration without rate
matcher
×4 bonded channel configuration
×8 bonded channel configuration
Non-bonded channel
configuration with rate matcher
Non-bonded channel
configuration without rate
matcher
×4 bonded channel configuration
×8 bonded channel configuration
Note to
(1) The clock signal driven on the rx_coreclk port must have 0 PPM frequency difference with respect to the receiver phase compensation FIFO
write clock.
Table
Configuration
Configuration
1–38:
The receiver phase compensation FIFO write clock source varies with the receiver
channel configuration.
clock source in different configurations.
The receiver phase compensation FIFO read clock source varies depending on
whether or not you instantiate the rx_coreclk port in the ALTGX MegaWizard
Plug-In Manager.
source in different configurations.
Parallel transmitter PCS clock from the
local clock divider in the associated
channel (tx_clkout)
Parallel recovered clock from the receiver
PMA in the associated channel
(rx_clkout)
Parallel transmitter PCS clock from the
central clock divider in the CMU0 of the
associated transceiver block
(coreclkout)
Parallel transmitter PCS clock from the
central clock divider in CMU0 of the master
transceiver block (coreclkout from
master transceiver block)
FPGA fabric clock driven by the clock
signal on the tx_clkout port
FPGA fabric clock driven by the clock
signal on the rx_clkout port
FPGA fabric clock driven by the clock
signal on the coreclkout port
FPGA fabric clock driven by the clock
signal on the coreclkout port
rx_coreclk Port Not Instantiated
Table 1–38
Without Byte Serializer
Table 1–37
Receiver Phase Compensation FIFO Write Clock
Receiver Phase Compensation FIFO Read Clock
lists the receiver phase compensation FIFO read clock
lists the receiver phase compensation FIFO write
Stratix IV Device Handbook Volume 2: Transceivers
Divide-by-two version of the parallel
transmitter PCS clock from the local clock
divider in the associated channel
(tx_clkout)
Divide-by-two version of the parallel
recovered clock from the receiver PMA in
the associated channel (rx_clkout)
Divide-by-two version of the parallel
transmitter PCS clock from the central
clock divider in CMU0 of the associated
transceiver block (coreclkout)
Divide-by-two version of the parallel
transmitter PCS clock from the central
clock divider in CMU0 of the master
transceiver block (coreclkout from
master transceiver block)
FPGA fabric clock driven by the clock
signal on the rx_coreclk port
FPGA fabric clock driven by the clock
signal on the rx_coreclk port
FPGA fabric clock driven by the clock
signal on the rx_coreclk port
FPGA fabric clock driven by the clock
signal on the rx_coreclk port
rx_coreclk Port Instantiated
With Byte Serializer
(1)
1–99
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