EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 838
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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4–32
Figure 4–18. Reset Sequence with CDR in Automatic Lock Mode
Notes to
(1) For t
(2) For t
Stratix IV Device Handbook Volume 2: Transceivers
Reset and Power Down Signals
Figure
pll_powerdown
LTD_Auto
Ouput Status Signals
4–18:
duration, refer to the
rx_analogreset[0]
pll_powerdown[0]
pll_powerdown[3]
rx_analogreset[3]
rx_freqlocked[0]
rx_dataout[63:0]
rx_freqlocked[3]
duration, refer to the
pll_locked[3]
pll_locked[0]
Receiver and Transmitter Channel Set-Up—Receiver CDR in Automatic Lock
Mode
This configuration contains both a transmitter and receiver channel. For Basic (PMA
Direct) drive ×1 mode, with receiver CDR in automatic lock mode, use the reset
sequence shown in
mode.
busy
DC and Switching Characteristics for Stratix IV Devices
1
t
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
2
Figure
3
3
4–18. In this example, four channels are configured in this
Minimum of Two Parallel Clock Cycles
4
5
5
Chapter 4: Reset Control and Power Down in Stratix IV Devices
chapter.
t
TLD_Auto (2)
6
6
chapter.
PMA Direct Drive Mode Reset Sequences
7
valid parallel data into FPGA fabric
February 2011 Altera Corporation
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