EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 936

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–90
Stratix IV Device Handbook Volume 2: Transceivers
PMA Controls Reconfiguration Duration When Using Method 1
The logical_channel_address port is used in Method 1. The write transaction and
read transaction duration is as follows:
For writing values to the following PMA controls, the busy signal is asserted for 260
reconfig_clk clock cycles for each of these controls:
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■
■
■
For writing values to the following PMA controls, the busy signal is asserted for 520
reconfig_clk clock cycles for each of these controls:
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■
For reading the existing values of the following PMA controls, the busy signal is
asserted for 130 reconfig_clk clock cycles for each of these controls. The data_valid
signal is then asserted after the busy signal goes low.
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■
■
■
For reading the existing values of the following PMA controls, the busy signal is
asserted for 260 reconfig_clk clock cycles for each of these controls. The data_valid
signal is then asserted after the busy signal goes low.
■
■
PMA Controls Reconfiguration Duration When Using Method 2 or Method 3
The logical_channel_address port is not used in Method 2 and Method 3. The write
transaction duration and read transaction duration are as follows:
For writing values to the following PMA controls, the busy signal is asserted for 260
reconfig_clk clock cycles per channel for each of these controls:
■
■
■
■
tx_preemp_1t (pre-emphasis control first post-tap)
tx_vodctrl (voltage output differential)
rx_eqctrl (equalizer control)
rx_eqdcgain (equalizer DC gain)
tx_preemp_0t (pre-emphasis control pre-tap)
tx_preemp_2t (pre-emphasis control second post-tap)
tx_preemp_1t_out (pre-emphasis control first post-tap)
tx_vodctrl_out (voltage output differential)
rx_eqctrl_out (equalizer control)
rx_eqdcgain_out (equalizer DC gain)
tx_preemp_0t_out (pre-emphasis control pre-tap)
tx_preemp_2t_out (pre-emphasis control second post-tap)
tx_preemp_1t (pre-emphasis control first post-tap)
tx_vodctrl (voltage output differential)
rx_eqctrl (equalizer control)
rx_eqdcgain (equalizer DC gain)
Write Transaction Duration
Read Transaction Duration
Write Transaction Duration
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
February 2011 Altera Corporation
Dynamic Reconfiguration Duration