EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 537

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–81. Byte Deserializer in Single-Width Mode
Figure 1–82. Byte Deserializer in Double-Width Mode
February 2011 Altera Corporation
dataout[15:0]
dataout[19:0]
datain[7:0]
datain[9:0]
or
or
In single-width mode, the byte deserializer receives 8-bit wide data from the 8B/10B
decoder or 10-bit wide data from the word aligner (if the 8B/10B decoder is disabled)
and deserializes it into 16-bit or 20-bit wide data at half the speed.
Figure 1–81
In double-width mode, the byte deserializer receives 16-bit wide data from the
8B/10B decoder or 20-bit wide data from the word aligner (if the 8B/10B decoder is
disabled) and deserializes it into 32-bit or 40-bit wide data at half the speed.
Figure 1–82
Byte Ordering Block
In single-width modes with the 16-bit or 20-bit FPGA fabric-transceiver interface, the
byte deserializer receives one data byte (8 or 10 bits) and deserializes it into two data
bytes (16 or 20 bits). Depending on when the receiver PCS logic comes out of reset, the
byte ordering at the output of the byte deserializer may or may not match the original
byte ordering of the transmitted data. The byte misalignment resulting from byte
deserialization is unpredictable because it depends on which byte is being received by
the byte deserializer when it comes out of reset.
which the MSByte and LSByte of the two-byte transmitter data appears straddled
across two word boundaries after getting byte deserialized at the receiver.
D1
D1D2
Byte Deserializer in Single-Width Mode
Byte Deserializer in Double-Width Mode
D2
Receiver PCS Clock
D3D4
Receiver PCS Clock
shows the byte deserializer in single-width mode.
shows the byte deserializer in double-width mode.
D3
D5D6 D7D8
D4
Deserializer
Deserializer
Byte
Byte
/2
/2
D2
D1
D1D2
D3D4
Figure 1–83
Stratix IV Device Handbook Volume 2: Transceivers
D4
D3
D7D8
D5D6
shows a scenario in
dataout[15:0]
dataout[19:0]
dataout[31:0]
dataout[39:0]
or
or
1–93