EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 527
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–66. Rate Match Deletion in GIGE Mode
Figure 1–67. Rate Match Insertion in GIGE Mode
February 2011 Altera Corporation
rx_rmfifodatadeleted
rx_rmfifodatainserted
dataout
datain
1
dataout
datain
The rate match FIFO can insert or delete as many /I2/ or /C2/ (first two bytes) as
necessary to perform the rate match operation.
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, that indicate rate
match FIFO deletion and insertion events, respectively, are forwarded to the FPGA
fabric. Both the rx_rmfifodatadeleted and rx_rmfifodatainserted flags are asserted
for two clock cycles for each deleted and inserted /I2/ ordered set, respectively.
Figure 1–66
symbols are required to be deleted. Because the rate match FIFO can only delete /I2/
ordered set, it deletes two /I2/ ordered sets (four symbols deleted).
Figure 1–67
symbol is required to be inserted. Because the rate match FIFO can only insert a /I2/
ordered set, it inserts one /I2/ ordered set (two symbols inserted).
Two flags, rx_rmfifofull and rx_rmfifoempty, are forwarded to the FPGA fabric to
indicate rate match FIFO full and empty conditions.
In GIGE mode, the rate match FIFO does not insert or delete code groups
automatically to overcome FIFO empty and full conditions, respectively. It asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least two recovered clock cycles to
indicate rate match FIFO full and empty conditions, respectively.
In the case of rate match FIFO full and empty conditions, you must assert the
rx_digitalreset signal to reset the receiver PCS blocks.
Dx.y
Dx.y
Dx.y
Dx.y
shows an example of rate match FIFO deletion in the case where three
First /I2/ Ordered Set
shows an example of rate match FIFO insertion in the case where one
K28.5
K28.5
First /I2/ Ordered Set
K28.5
K28.5
D16.2
D16.2
D16.2
D16.2
/I2/ Ordered Set Deleted
Second /I2/ Ordered Set
Second /I2/ Ordered Set
K28.5
K28.5
Dx.y
K28.5
D16.2
D16.2
D16.2
Stratix IV Device Handbook Volume 2: Transceivers
K28.5
Third /I2/ Ordered Set
K28.5
D16.2
D16.2
Dx.y
Dx.y
1–83
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