EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 883

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
f
1
There are two signals available when you enable the Channel Interface option:
■
■
In addition to these two ports, you can select the necessary control and status signals
for the reconfigured channel in the Clocking/Interface screen.
For more information about control and status signals, refer to the “Transceiver Port
Lists” section in the
These control and status signals are not applicable in Basic (PMA Direct) functional
mode.
option.
Table 5–8. Control and Status Signals Not Applicable in Basic (PMA Direct) Mode with the
Channel Interface Option Enabled
The Quartus II software has legal checks for the connectivity of tx_datainfull and
rx_dataoutfull and the various control and status signals you enable in the
Clocking/Interface screen.
For example, the Quartus II software allows you to select and connect the pipestatus
and powerdn signals. It assumes that you are planning to switch to and from PCIe
functional mode.
channel interface signals.
tx_datainfull—The width of this input signal depends on the number of
channels you set up in the General screen. It is 44 bits wide per channel. This
signal is available only for Transmitter only and Receiver and Transmitter
configurations. This port replaces the existing tx_datain port.
rx_dataoutfull—The width of this output signal depends on the number of
channels you set up in the General screen. It is 64 bits wide per channel. This
signal is available only for Receiver only and Receiver and Transmitter
configurations. This port replaces the existing rx_dataout port.
FPGA Fabric-Receiver Interface
Table 5–8
rx_patterndetect
rx_a1a2sizeout
rx_syncstatus
rx_ctrldetect
rx_errdetect
rx_dataout
rx_disperr
lists the signals not available when you enable the Channel Interface
Table 5–9
Transceiver Architecture in Stratix IV Devices
lists the tx_datainfull[43:0] FPGA fabric-transceiver
FPGA Fabric-Transmitter Interface
Stratix IV Device Handbook Volume 2: Transceivers
tx_ctrlenable
tx_forcedisp
tx_dispval
tx_datain
chapter.
5–37