EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 192

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–20
Stratix IV Device Handbook Volume 1
High-Speed Differential I/O with DPA Support
Programmable Current Strength
f
Stratix IV devices have the following dedicated circuitry for high-speed differential
I/O support:
■
■
■
■
■
■
■
For more information about DPA support, refer to the
Interfaces and DPA in Stratix IV Devices
The output buffer for each Stratix IV device I/O pin has a programmable current
strength control for certain I/O standards. Use programmable current strength to
mitigate the effects of high signal attenuation due to a long transmission line or a
legacy backplane. The LVTTL, LVCMOS, SSTL, and HSTL standards have several
levels of current strength that you can control.
current strength for Stratix IV devices.
Table 6–3. Programmable Current Strength (Part 1 of 2)
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
Dynamic phase aligner (DPA)
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs)
I/O Standard
I
OH
chapter.
/ I
Setting (mA) for
Column I/O Pins
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
12, 10, 8, 6, 4
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
Current Strength
8, 6, 4, 2
12, 10, 8
16, 8
16, 8
16
16
16
Table 6–3
(Note
Chapter 6: I/O Features in Stratix IV Devices
High-Speed Differential I/O
1),
lists the programmable
(2)
February 2011 Altera Corporation
I
OH
/ I
Setting (mA) for
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
Row I/O Pins
Current Strength
8, 6, 4, 2
8, 6, 4, 2
12, 8, 4
12, 8, 4
8, 6, 4
8, 6, 4
12, 8
16, 8
8, 4
4, 2
16
—
16
—
I/O Structure