EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 290

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–12
Stratix IV Device Handbook Volume 1
The load enable (LVDS_LOAD_EN) signal and the diffioclk signal (the clock running at
serial data rate) generated from PLL_Lx (left PLL) or PLL_Rx (right PLL) clocks the load
and shift registers. You can statically set the serialization factor to ×3, ×4, ×6, ×7, ×8, or
×10 using the Quartus II software. The load enable signal is derived from the
serialization factor setting.
transmitter.
Figure 8–5. Stratix IV Transmitter
Notes to
(1) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(2) The tx_in port has a maximum data width of 10 bits.
You can configure any Stratix IV transmitter data channel to generate a
source-synchronous transmitter clock output. This flexibility allows the placement of
the output clock near the data outputs to simplify board layout and reduce
clock-to-data skew. Different applications often require specific clock-to-data
alignments or specific data-rate-to-clock-rate factors. The transmitter can output a
clock signal at the same rate as the data with a maximum frequency of 800 MHz. The
output clock can also be divided by a factor of 1, 2, 4, 6, 8, or 10, depending on the
serialization factor. You can set the phase of the clock in relation to the data at 0° or
180° (edge or center aligned). The left and right PLLs (PLL_Lx and PLL_Rx) provide
additional support for other phase shifts in 45° increments. These settings are made
statically in the Quartus II MegaWizard Plug-In Manager software.
tx_coreclock
Figure
Fabric
FPGA
tx_in 10
8–5:
Left/Right PLL
DIN
Serializer
3
DOUT
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Figure 8–5
2
(Note
IOE
1),
tx_inclock
shows a block diagram of the Stratix IV
(2)
LVDS Transmitter
IOE supports SDR, DDR, or
Non-Registered Datapath
February 2011 Altera Corporation
LVDS Clock Domain
Differential Transmitter
+
-
tx_out