EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 701

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Table 2–7. Transmitter Datapath Clock Frequencies in ×4 Bonded Functional Modes
February 2011 Altera Corporation
PCIe ×4 (Gen 1)
PCIe ×4 (Gen 2)
XAUI
Functional Mode
f
1
The transceiver clocks are distributed to the four bonded channels on the ×4
high-speed serial and ×4 low-speed parallel clock lines. The serializer in the
transmitter channel PMA of the four bonded channels uses the same low-speed
parallel clock and high-speed serial clock from CMU0 Channel for their
parallel-in-serial-out operation. The low-speed parallel clock clocks the 8B/10B
encoder and the write port of the byte serializer (if enabled) in the transmitter channel
PCS.
Depending on whether the you use the byte serializer or not, the low-speed parallel
clock (when you do not use the byte serializer) or a divide-by-two version of the
low-speed parallel clock (when you use the byte serializer) from the CMU0 clock
divider block clocks the read port of the transmitter phase compensation FIFO in all
four bonded channels. This clock is driven directly on the coreclkout port as the
FPGA fabric-Transceiver interface clock. You can use the coreclkout signal to clock
the transmitter data and control logic in the FPGA fabric for all four bonded channels.
The ATX PLL block drives the high-speed serial clock and low-speed parallel clock to
the transmitter channels on the ×N_Top or ×N_Bottom lines.
For more information, refer to the
Stratix IV Devices
In ×4 PCS and PMA bonded channel configurations, the transmitter phase
compensation FIFOs in all four bonded channels share common read and write
pointers and enable signals generated in the CMU0 channel of the transceiver block.
This ensures equal transmitter phase compensation FIFO latency across all four
bonded channels, resulting in low transmitter channel-to-channel skew.
Table 2–3
modes that have a fixed data rate.
The following functional modes support ×8 PCS and PMA bonded transmitter
channel configuration:
■
■
Use either the CMU PLL or the ATX PLL to generate the transceiver clocks in Basic ×8
functional modes. Use the ATX PLL in PCIe ×8 Gen2 mode in order to meet the
transmitter jitter compliance.
Data Rate (Gbps)
PCIe ×8—Gen1 and Gen2
Basic ×8
×8 PCS and PMA Bonded Channel Configuration
3.125
2.5
5
lists the transmitter datapath clock frequencies in ×4 bonded functional
chapter.
High-Speed Serial
Clock Frequency
1.5625
(GHz)
1.25
2.5
Configuring Multiple Protocols and Data Rates in
Frequency (MHz)
Parallel Clock
Low-Speed
312.5
250
500
Stratix IV Device Handbook Volume 2: Transceivers
Without Byte
Interface Clock Frequency
Serializer
FPGA Fabric-Transceiver
(MHz)
250
N/A
N/A
With Byte
Serializer
156.25
(MHz)
125
250
2–29