EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 694

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–22
Stratix IV Device Handbook Volume 2: Transceivers
Transmitter Channel Datapath Clocking Resources
The Stratix IV transceivers support various non-bonded and bonded transceiver
clocking configurations through the dedicated ×1, ×4, and ×N high-speed serial and
low-speed parallel clock lines.
Figure 2–13
modes.
Figure 2–13. Transceiver Clock Distribution in the Stratix IV GT EP4S100G5F45 and Stratix IV GX
EP4SGX530KF40 Devices
Note to
(1) The 10G ATX PLL block is not available for the EP4SGX530KF40 device.
Table
2–14:
shows the transceiver clock distribution in ×1, ×4, ×8, and ×N bonded
Transceiver Block GXBR2
Transceiver Block GXBR3
Transceiver Block GXBR1
Transceiver Block GXBR0
ATX PLL Block (10G) (1)
ATX PLL Block (6G)
ATX PLL Block (6G)
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
Channel 1
Channel 0
Channel 3
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 2
Channel 3
Channel 2
CMU1 GXBR2
CMU1 GXBR3
CMU1 GXBR1
CMU1 GXBR0
x1
x1
x1
x1
CMU0 GXBR3
CMU0 GXBR0
CMU0 GXBR1
CMU0 GXBR2
x1
x1
x1
x1
x4 GXBR3
x4 GXBR2
x4 GXBR1
Chapter 2: Transceiver Clocking in Stratix IV Devices
x4 GXBR0
xN_Bottom
Transceiver Channel Datapath Clocking
xN_Top
February 2011 Altera Corporation