EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 811

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
Figure 4–2. Transceiver Reset Sequences Chart
Notes to
(1) Refer to the Timing Diagram in
(2) Refer to the Timing Diagram in
(3) Refer to the Timing Diagram in
(4) Refer to the Timing Diagram in
(5) Refer to the Timing Diagram in
(6) Refer to the Timing Diagram in
(7) Refer to the Timing Diagram in
(8) Refer to the Timing Diagram in
(9) Refer to the Timing Diagram in
(10) Refer to the Timing Diagram in
(11) Refer to the Timing Diagram in
(12) Refer to the Timing Diagram in
(13) Refer to the Timing Diagram in
(14) Refer to the Timing Diagram in
(15) Refer to the Timing Diagram in
February 2011 Altera Corporation
Reset Sequence
the data rate of
the transceiver
to change
channel
Figure
Dynamic Reconfiguration
4–2:
1
1
the TX PLL settings
Reset Sequence
the transceiver
to change
The busy signal remains low for the first reconfig_clk clock cycle. It then is asserted
from the second reconfig_clk clock cycle. Subsequent de-assertion of the busy signal
indicates the completion of the offset cancellation process. This busy signal is required
in transceiver reset sequences except for Transmitter Only channel configurations.
For more information, refer to the reset sequences shown in
associated references listed in the figure notes.
Altera strongly recommends adhering to these reset sequences for proper operation of
the Stratix IV transceiver.
Figure 4–2
channel
Receiver CDR
in automatic
lock mode
‘Transmitter Only’
channel (2)
(3)
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Receiver CDR
Bonded
in manual
lock mode
4–12.
4–3.
4–4.
4–5.
4–6.
4–7.
4–8.
4–9.
4–10.
4–11.
4–13.
4–16.
4–17.
4–18.
4–19.
(4)
shows the transceiver reset sequences for Stratix IV devices.
‘Receiver and
Transmitter’
channel
and PMA Direct Drive Mode
Receiver CDR
except PCI Express (PIPE)
in automatic
lock mode
functional modes
All supported
(5)
‘Transmitter Only’
Receiver CDR
channel (2)
lock mode
in manual
(6)
Non-Bonded
initialization reset
Transceiver
sequences
Receiver CDR
in automatic
lock mode
(7)
‘Receiver Only’
channel
Receiver CDR
lock mode
Normal Operation
in manual
Compliance and
Initialization/
Phases (1)
(8)
PCI Express
(PIPE)
Receiver CDR
in automatic
lock mode
(9)
‘Receiver and
Transmitter’
channel
Receiver CDR
Stratix IV Device Handbook Volume 2: Transceivers
lock mode
in manual
(10)
‘Transmitter Only’
channel (11)
Receiver CDR in
automatic lock
mode (12)
Figure 4–2
xN
‘Receiver and
Transmitter’
channel
Receiver CDR in
manual lock
mode (13)
PMA Direct
Drive
and the
Receiver CDR in
automatic lock
mode (14)
‘Receiver and
Transmitter’
channel
x1
Receiver CDR in
4–5
manual lock
mode (15)