EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 1038

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–20
Table 2–6. Configuring Clocking (Part 2 of 2)
Figure 2–3. Top-Level Transceiver Setup—Transmitter-Side Only
Stratix IV Device Handbook Volume 3
Can transceiver-FPGA fabric interface clocking be shared?
Does the Stratix IV GX transceiver support this feature?
refclk1 (53.125 MHz)
refclk0 (106.25 MHz)
f
1
For more information about clocking the transmitter and receiver channel data path
for this type of configuration, refer to the “Transmitter Channel Datapath Clocking”
section of the
Figure 2–3
The transmitter side receives its clocks from the clock multiplier unit (CMU) PLLs.
The receiver side contains its dedicated CDR that provides the high-speed serial and
low-speed parallel clocks to its PMA and PCS blocks, respectively.
Questions
shows the transmitter side of the transceiver setup for Example 1.
Second CMU PLL Configured for
Transceiver Clocking in Stratix IV Devices
One CMU PLL Configured for
1.0625 Gbps Data Rate
4.25 Gbps Data Rate
Transceiver Block
No
The design requires independent control on all channels, so
you must not share the transceiver-FPGA fabric interface
clock of one channel with another channel. Each of the
channels must use its own tx_clkout and rx_clkout
signals to clock the data between the transceiver channels and
the FPGA fabric.
Yes
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
chapter.
Answer
(1.0625 Gbps)
(4.25 Gbps)
(4.25 Gbps)
February 2011 Altera Corporation
Channel 1
Channel 2
Channel 0
TX
TX
RX
RX
TX