EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 130

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

5–24
18 × 18 Complex Multiply
Figure 5–16. Complex Multiplier Using Two-Multiplier Adder Mode
Stratix III Device Handbook, Volume 1
A
B
C
D
You can configure the DSP block when used in Two-Multiplier Adder mode to
implement complex multipliers using the two-multiplier adder mode. A single half
DSP block can implement one 18-bit complex multiplier.
A complex multiplication can be written as shown in
Equation 5–4. Complex Multiplication Equation
To implement this complex multiplication within the DSP block, the real part
((a × c) – (b × d)) is implemented using two multipliers feeding one subtractor block
while the imaginary part ((a × d) + (b × c)) is implemented using another two
multipliers feeding an adder block.
multiplication. This mode automatically assumes all inputs are using signed
numbers.
clock[3..0]
ena[3..0]
aclr[3..0]
Half-DSP Block
(a + jb) × (c + jd) = ((a × c) – (b × d)) + j((a × d) + (b × c))
signa
signb
−
+
Figure 5–16
shows an 18-bit complex
36
36
Chapter 5: DSP Blocks in Stratix III Devices
Equation
(Imaginary Part)
(A
(A
(Real Part)
x
x
C) − (B
D) − (B
© March 2010 Altera Corporation
5–4.
Operational Mode Descriptions
x
x
D)
C)