EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 151

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
Clock Networks in Stratix III Devices
Figure 6–2. Regional Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices)
Figure 6–3. Regional Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices)
© July 2010
Altera Corporation
Regional Clock Networks
The regional clock (RCLK) networks only pertain to the quadrant they drive into. The
RCLK networks provide the lowest clock delay and skew for logic contained within a
single device quadrant. Stratix III device I/O elements and internal logic within a
given quadrant can also drive RCLKs to create internally generated regional clocks
and other high fan-out control signals; for example, synchronous or asynchronous
clears and clock enables.
drive RCLK networks in Stratix III devices. The EP3SL50, EP3SL70, EP3SL110,
EP3SL150, EP3SE50, EP3SE80, and EP3SE110 devices contain 64 RCLKs; the
EP3SL200, EP3SE260, and EP3SL340 devices contain 88 RCLKs.
CLK[0..3]
CLK[0..3]
L2
L2
L3
RCLK[6..11]
RCLK[0..5]
RCLK[6..11]
RCLK[0..5]
RCLK[12..21]
RCLK[54..63]
RCLK[54..63] RCLK[44..53]
RCLK[12..21] RCLK[22..31]
Figure 6–2
CLK[12..15]
CLK[12..15]
Q1
Q4
CLK[4..7]
CLK[4..7]
Q1 Q2
Q4 Q3
T1
B1
T1
B1
B2
Q2
Q3
T2
RCLK[44..53]
RCLK[22..31]
to
Figure 6–4
RCLK[38..43]
RCLK[32..37]
RCLK[38..43]
RCLK[32..37]
show CLK pins and PLLs that can
R2
R2
R3
CLK[8..11]
CLK[8..11]
Stratix III Device Handbook, Volume 1
6–3