EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 338

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–6
Design Security Using Configuration Bitstream Encryption
Stratix III Device Handbook, Volume 1
f
1
Figure 11–2. Compressed and Uncompressed Configuration Data in the Same Configuration File
To generate programming files for this setup in the Quartus II software, on the File
menu, click Convert Programming Files.
Stratix III devices support decryption of configuration bitstreams using the advanced
encryption standard (AES) algorithm—the most advanced encryption algorithm
available today. Both non-volatile and volatile key programming are supported using
Stratix III devices. When using the design security feature, a 256-bit security key is
stored in the Stratix III device. To successfully configure a Stratix III device that has
the design security feature enabled, the device must be configured with a
configuration file that was encrypted using the same 256-bit security key. Non-volatile
key programming does not require any external devices, such as a battery backup, for
storage. However, for certain applications, you can store the security keys in volatile
memory in the Stratix III device. An external battery is needed for this volatile key
storage.
When using a serial configuration scheme such as PS or fast AS, configuration time is
the same whether or not the design security feature is enabled. If the FPP scheme is
used with the design security or decompression feature, a ×4 DCLK is required. This
results in a slower configuration time when compared to the configuration time of a
Stratix III device that has neither the design security nor the decompression feature
enabled.
For more information about this feature, refer to the
Devices
chapter in volume 1 of the Stratix III Device Handbook.
GND
Configuration
Compressed
Data
nCE
Decompression
Controller
Stratix III
FPGA
nCEO
Uncompressed
Configuration
Data
nCE
Stratix III
FPGA
Serial Configuration Data
nCEO
Design Security in Stratix III
Chapter 11: Configuring Stratix III Devices
N.C.
© March 2011 Altera Corporation
Serial Configuration
Device
Configuration Features