EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 135

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 5: DSP Blocks in Stratix III Devices
Operational Mode Descriptions
Shift Modes
© March 2010 Altera Corporation
1
1
A single DSP block can implement up to two independent 44-bit accumulators.
The dynamic accum_sload control signal is used to clear the accumulation. A
logic 1 value on the accum_sload signal synchronously loads the accumulator
with the multiplier result only, while a logic 0 enables accumulation by adding or
subtracting the output of the DSP block (accumulator feedback) to the output of the
multiplier and first-stage adder.
The control signal for the accumulator and subtractor is static and therefore has to be
configured at compile time.
This mode supports the round and saturation logic unit as it is configured as an 18-bit
multiplier accumulator. You can use the pipeline registers and output registers within
the DSP block to increase the performance of the DSP block.
Stratix III devices support the following shift modes for 32-bit input only:
■
■
■
■
■
You can switch the shift mode between these modes using the dynamic rotate and
shift control signals.
The shift mode in a Stratix III device can be easily used by the soft embedded
processor such as Nios
Figure 5–20
The shift mode makes use of the available multipliers to logically or arithmetically
shift left, right, or rotate the desired 32-bit data. The DSP block is configured like the
independent 36-bit multiplier mode to perform the shift mode operations.
The arithmetic shift right requires signed input vector. During arithmetic shift right,
the sign is extended to fill the MSB of the 32-bit vector. The logical shift right uses
unsigned input vector. During logical shift right, zeros are padded in the most
significant bits shifting the 32-bit vector to the right. The barrel shifter uses unsigned
input vector and implements a rotation function on a 32-bit word length.
Two control signals rotate and shift_right together with the signa and signb
signals, determining the shifting operation. Examples of shift operations are listed in
Table 5–5 on page
Arithmetic shift left, ASL[N]
Arithmetic shift right, ASR[32-N]
Logical shift left, LSL[N]
Logical shift right, LSR[32-N]
32-bit rotator or Barrel shifter, ROT[N]
shows the shift mode configuration.
5–31.
®
II to perform the dynamic shift and rotate operation.
Stratix III Device Handbook, Volume 1
5–29