EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 235

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 7: Stratix III Device I/O Features
OCT Calibration
Figure 7–18. OCT User-Mode Signal Timing Waveform for One OCT Block
Note to
(1) ts2p ≥ 25 ns
© July 2010
Figure
Altera Corporation
7–18:
OCTUSRCLK
S2PENA_1A
nCLRUSR
OCT Calibration
Figure 7–18
block[N] (where N is a calibration block number), you must assert ENAOCT one cycle
before asserting ENASER[N]. Also, nCLRUSR must be set to low for one OCTUSRCLK
cycle before ENASER[N] signal is asserted. An asserted ENASER[N] signals for 1000
OCTUSRCLK cycles to perform OCTR
deasserted one clock cycle after the last ENASER is deasserted.
Serial Data Transfer
When calibration is complete, you must serially shift out the 28-bit OCT calibration
code (14-bit OCT RS code and 14-bit OCT RT) from each OCT calibration block to the
corresponding I/O buffers. Only one OCT calibration block can send out the codes at
any given time by asserting only one ENASER[N] signal at a time. After ENAOCT is
deasserted, you must wait at least 1 OCTUSRCLK cycle to enable any ENASER[N]
signal to begin serial transfer. To shift 28-bit code from OCT calibration block[N],
ENASER[N] must be asserted for exactly 28 OCTUSRCLK cycles. There must be at least
one OCTUSRCLK cycle gap between two consecutive asserted ENASER signals. For
these requirements, refer to
After calibrated codes are shifted serially to the corresponding I/O buffers, they must
be converted from serial format to parallel format before being used in the I/O
buffers.
the calibration codes in each I/O bank. All I/O banks that received the codes from the
same OCT calibration block can have S2PENA asserted at the same time, or at a
different time, even while another OCT calibration block is calibrating and serially
shifting codes. The S2PENA signal is asserted one OCTUSRCLK cycle after ENASER is
deasserted for at least 25 ns. You cannot use I/Os for transmitting or receiving data
when their S2PENA is asserted for parallel codes transfer.
Example of Using Multiple OCT Calibration Blocks
Figure 7–19
and R
asserting ENASER signals at different times. ENAOCT must stay asserted while any
calibration is ongoing. nCLRUSR must be set to low for one OCTUSRCLK cycle before
each ENASER[N] signal is asserted. In
second time to initialize OCT calibration block 0, this does not affect OCT calibration
block 1, whose calibration is already in progress.
ENASER0
ENAOCT
T
calibration. Calibration blocks can start calibrating at different times by
Figure 7–18
shows the user-mode signal-timing waveforms. To calibrate OCT
shows a signal timing waveform for two OCT calibration blocks doing R
(1000 OCTUSRCLK cycles)
Calibration Phase
shows S2PENA signals that can be asserted at any time to update
Figure
7–18.
S
and OCTR
Figure
OCTUSRCLK
Cycles
7–19, when nCLRUSR is set to 0 for the
28
T
calibration. ENAOCT can be
t s2p
(1)
Stratix III Device Handbook, Volume 1
7–31
S