EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 402
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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13–4
IEEE Std. 1149.1 Boundary-Scan Register
Stratix III Device Handbook, Volume 1
f
The boundary-scan register is a large serial shift register that uses the TDI pin as an
input and the TDO pin as an output. The boundary-scan register consists of three-bit
peripheral elements that are associated with Stratix III I/O pins. You can use the
boundary-scan register to test external pin connections or to capture internal data.
For the Stratix III family device boundary-scan register lengths, refer to the
Configuring Stratix III Devices
Figure 13–3
Std. 1149.1 device.
Figure 13–3. Boundary-Scan Register
Table 13–2
Table 13–2. Stratix III Boundary-Scan Register Length
lists the boundary-scan register length for Stratix III devices.
shows how test data is serially shifted around the periphery of the IEEE
EP3SL150ES
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE110
EP3SE260
EP3SL50
EP3SL70
EP3SE50
EP3SE80
TDI
Device
TMS
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
chapter in volume 1 of the Stratix III Device Handbook.
TAP Controller
Internal Logic
TCK
TRST
TDO
Boundary-Scan Register Length
Each peripheral
element is either an
I/O pin, dedicated
input pin, or
dedicated
configuration pin.
IEEE Std. 1149.1 Boundary-Scan Register
© July 2010 Altera Corporation
1506
1506
2274
2274
2274
2970
3402
1506
2274
2274
2970
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