EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 180

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

6–32
Post-Scale Counter Cascading
Figure 6–31. Counter Cascading
Note to
(1) n = 6 or n = 9
Programmable Duty Cycle
Stratix III Device Handbook, Volume 1
Figure
6–31:
1
The Stratix III PLLs support post-scale counter cascading to create counters larger
than 512. This is automatically implemented in the Quartus II software by feeding the
output of one C counter into the input of the next C counter as shown in
When cascading post-scale counters to implement a larger division of the
high-frequency VCO clock, the cascaded counters behave as one counter with the
product of the individual counter settings. For example, if C0 = 40 and C1 = 20, then
the cascaded value is C0*C1 = 800.
Post-scale counter cascading is set in the configuration file. It cannot be done using
PLL reconfiguration.
The programmable duty cycle allows PLLs to generate clock outputs with a variable
duty cycle. This feature is supported on the PLL post-scale counters. The duty-cycle
setting is achieved by a low and high time-count setting for the post-scale counters.
The Quartus II software uses the frequency input and the required multiply or divide
rate to determine the duty cycle choices. The post-scale counter value determines the
precision of the duty cycle. The precision is defined by 50% divided by the post-scale
counter value. For example, if the C0 counter is 10, then steps of 5% are possible for
duty-cycle choices between 5% to 90%.
If the PLL is in external feedback mode, you must set the duty cycle for the counter
driving the fbin pin to 50%. Combining the programmable duty cycle with
programmable phase shift allows the generation of precise non-overlapping clocks.
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
C0
C1
C2
C3
C4
Cn
(1)
Chapter 6: Clock Networks and PLLs in Stratix III Devices
from preceding
post-scale counter
© July 2010 Altera Corporation
PLLs in Stratix III Devices
Figure
6–31.