EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 150

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

6–2
Figure 6–1. Global Clock Networks
Stratix III Device Handbook, Volume 1
Table 6–1. Clock Resources in Stratix III Devices (Part 2 of 2)
Stratix III devices have up to 32 dedicated single-ended clock pins or 16 dedicated
differential clock pins (CLK[0:15]p and CLK[0:15]n) that can drive either the
GCLK or RCLK networks. These clock pins are arranged on the four sides of the
Stratix III device, as shown in
Global Clock Networks
Stratix III devices provide up to 16 GCLKs that can drive throughout the entire
device, serving as low-skew clock sources for functional blocks such as adaptive logic
modules (ALMs), digital signal processing (DSP) blocks, TriMatrix memory blocks,
and PLLs. Stratix III device I/O elements (IOEs) and internal logic can also drive
GCLKs to create internally generated global clocks and other high fan-out control
signals; for example, synchronous or asynchronous clears and clock enables.
Figure 6–1
devices.
GCLKs/RCLKs per device
Notes to
(1) There are 64 RCLKs in EP3SL50, EP3SL70, EP3SL110, EP3SL150, EP3SE50, EP3SE80, and EP3SE110 devices.
(2) There are 56 PCLKs in EP3SL50, EP3SL70, and EP3SE50 devices. There are 88 PCLKs in EP3SL110, EP3SL150,
(3) There are 32 GCLKs/RCLKs per quadrant in EP3SL50, EP3SL70, EP3SL110, EP3SL150, EP3SE50, EP3SE80, and
(4) There are 80 GCLKs/RCLKs per entire device in EP3SL50, EP3SL70, EP3SL110, EP3SL150, EP3SE50, EP3SE80,
There are 88 RCLKs in EP3SL200, EP3SE260, and EP3SL340 devices.
EP3SL200, EP3SE80, and EP3SE110 devices. There are 112 PCLKs in EP3SE260 and 132 PCLKs in the EP3SL340
device.
EP3SE110 devices. There are 38 GCLKs/RCLKs per quadrant in EP3SL200, EP3SE260, and EP3SL340 devices.
and EP3SE110 devices. There are 104 GCLKs/RCLKS per entire device in EP3SL200, EP3SE260, and EP3SL340
devices.
CLK[0..3]
Clock Resource
Table
shows CLK pins and PLLs that can drive GCLK networks in Stratix III
L1
L2
L3
L4
6–1:
GCLK[0..3]
GCLK[12..15]
GCLK[4..7]
CLK[12..15]
CLK[4..7]
80/104
T1 T2
Figure 6–1
B1 B2
# of Resources Available
(4)
GCLK[8..11]
to
Chapter 6: Clock Networks and PLLs in Stratix III Devices
Figure
R1
R2
R3
R4
6–4.
CLK[8..11]
16 GCLKs + 64 RCLKs /
16 GCLKs + 88 RCLKs
Clock Networks in Stratix III Devices
Source of Clock Resource
© July 2010 Altera Corporation