EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 179

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
PLLs in Stratix III Devices
Clock Multiplication and Division
© July 2010
Altera Corporation
Figure 6–30
clocks in EFB mode.
Figure 6–30. Phase Relationship Between PLL Clocks in External-Feedback Mode
Note to
(1) The PLL clock outputs can lead or lag the fbin clock input.
Each Stratix III PLL provides clock synthesis for PLL output ports using
m/(n* post-scale counter) scaling factors. The input clock is divided by a pre-scale
factor, n, and is then multiplied by the m feedback factor. The control loop drives the
VCO to match f
down the high-frequency VCO. For multiple PLL outputs with different frequencies,
the VCO is set to the least common multiple of the output frequencies that meets its
frequency specifications. For example, if output frequencies required from one PLL
are 33 and 66 MHz, then the Quartus II software sets the VCO to 660 MHz (the least
common multiple of 33 and 66 MHz within the VCO range). Then the post-scale
counters scale down the VCO frequency for each output port.
Each PLL has one pre-scale counter, n, and one multiply counter, m, with a range of 1
to 512 for both m and n. The n counter does not use duty-cycle control because the
only purpose of this counter is to calculate frequency division. There are seven generic
post-scale counters per Left/Right PLL and ten post-scale counters per Top/Bottom
PLL that can feed GCLKs, RCLKs, or external clock outputs. These post-scale counters
range from 1 to 512 with a 50% duty cycle setting. The high- and low-count values for
each counter range from 1 to 256. The sum of the high- and low-count values chosen
for a design selects the divide value for a given counter.
The Quartus II software automatically chooses the appropriate scaling factors
according to the input frequency, multiplication, and division values entered into the
ALTPLL megafunction.
Figure
6–30:
shows an example waveform of the phase relationship between PLL
fbin Clock Input Pin
Clock Outputs (1)
in
Dedicated PLL
(m/n). Each output port has a unique post-scale counter that divides
Clock Port (1)
PLL Clock at
the Register
PLL Reference
Clock at the
Input Pin
Phase Aligned
Stratix III Device Handbook, Volume 1
6–31