EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 67

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Introduction
Row Interconnects
© October 2008 Altera Corporation
SIII51003-1.2
Stratix
implement custom logic. A series of column and row interconnects of varying length
and speed provides signal interconnects between logic array blocks (LABs), memory
block structures, digital signal processing (DSP) blocks, and input/output elements
(IOE). These blocks communicate with themselves and to one another through a
fabric of routing wires. This chapter provides details on the Stratix III core routing
structure. It also describes how Stratix III block types interface to this fabric.
In the Stratix III architecture, connections between adaptive logic modules (ALMs),
TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack
interconnect structure with DirectDrive technology. The MultiTrack interconnect
consists of continuous, performance-optimized routing lines of different lengths and
speeds used for inter- and intra-design block connectivity. The Quartus
automatically routes critical design paths on faster interconnects to improve design
performance.
DirectDrive technology is a deterministic routing technology that ensures identical
routing resource usage for any function regardless of placement in the device. The
MultiTrack interconnect and DirectDrive technology simplify the integration stage of
block-based designing by eliminating the re-optimization cycles that typically follow
design changes and additions.
The MultiTrack interconnect consists of row and column interconnects that span fixed
distances. A routing structure with fixed length resources for all devices allows
predictable and repeatable performance when migrating through different device
densities.
Dedicated row interconnects route signals to and from LABs, DSP blocks, and
TriMatrix memory blocks in the same row. These row interconnect resources include:
■
■
■
The direct link interconnect allows a LAB, DSP block, or TriMatrix memory block to
drive into the local interconnect of its left and right neighbors. This capability
provides fast communication between adjacent LABs and blocks without using row
interconnect resources. The direct link interconnect is the fastest way to communicate
between two adjacent blocks.
The R4 interconnects span a combination of four LABs, memory logic array blocks
(MLAB), DSP blocks, M9K blocks, and M144K blocks. Use these resources for fast row
connections in a four-LAB region.
a LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and
row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
R20 row interconnects for high-speed access across the length of the device
®
III devices contain a two-dimensional row- and column-based architecture to
3. MultiTrack Interconnect in Stratix III
Figure 3–1
shows R4 interconnect connections from
Stratix III Device Handbook, Volume 1
®
II Compiler
Devices