EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 249

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

8. External Memory Interfaces in
Stratix III Devices
SIII51008-1.9
The Stratix
III I/O structure has been completely redesigned to provide flexible,
®
high-performance support for existing and emerging external memory standards.
These include high-performance double data rate (DDR) memory standards such as
DDR3, DDR2, DDR SDRAM, QDR II+, QDR II SRAM, and RLDRAM II.
Packed with features such as dynamic on-chip termination (OCT), trace mismatch
compensation, read and write leveling, half data rate (HDR) blocks, and 4- to 36- bit
programmable DQ group widths, Stratix III I/O elements provide easy-to-use built-in
functionality required for a rapid and robust implementation.
DDR external memory support is found on all sides of the Stratix III FPGA. Stratix III
devices provide an efficient architecture to quickly and easily fit wide
external–memory interfaces with the new small modular I/O bank structure.
A self-calibrating megafunction (ALTMEMPHY) is optimized to take advantage of the
Stratix III I/O structure, along with the Quartus
II software’s TimeQuest Timing
®
Analyzer, which provides the total solution for the highest reliable frequency of
operation across process, voltage, and temperature (PVT) variations.
f
While this chapter describe the silicon capability of Stratix III devices, for more
information about the external memory system specifications, implementation, board
guidelines, timing analysis, simulation, and design debugging, refer to the
Literature: External Memory Interfaces
section of the Altera website.
© March 2010
Altera Corporation
Stratix III Device Handbook, Volume 1