EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 92

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

4–12
Figure 4–10. Timing Waveform for Read-Write Operations (Single-Port Mode) for M9K and M144K
Figure 4–11. Timing Waveform for Read-Write Operations (Single-Port Mode) for MLABs
Simple Dual-Port Mode
Stratix III Device Handbook, Volume 1
q_a (asynch)
q_a (asynch)
address_a
address_a
Figure 4–10
mode with unregistered outputs for M9K and M144K. In M9K and M144K registering
the RAM’s outputs would simply delay the q output by one clock cycle.
Figure 4–11
mode with unregistered outputs for MLABs. For MLABs, the read operation is
triggered by the rising clock edges whereas the write operation is triggered by the
falling clock edges.
All TriMatrix memory blocks support simple dual-port mode. Simple dual-port mode
allows you to perform one-read and one-write operation to different locations at the
same time.
data_a
data_a
wrena
rdena
wrena
rdena
clk_a
clk_a
Figure 4–12
shows the timing waveforms for read and write operations in single-port
shows the timing waveforms for read and write operations in single-port
(old data
A
A
a0(old data)
a0
)
shows the simple dual-port configuration.
A
a0
a0
B
B
A
C
C
B
Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
B
C
D
D
(old data)
a1(old data)
a1
a1
a1
E
E
D
D
F
F
E
© May 2009 Altera Corporation
E
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