SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet
SAF-C161U-LF V1.3
Specifications of SAF-C161U-LF V1.3
SAFC161ULFV13XP
SP000007502
Related parts for SAF-C161U-LF V1.3
SAF-C161U-LF V1.3 Summary of contents
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... Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... Improved formatting (text, figures, tables) 1) All previous distributed versions are preliminary. They have been replaced by this version. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com 2001-04 Preliminary Data Sheet 02 ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 7.8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 12 Asynchronous/Synchr. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . 253 12.1 Functional Description . . . . . ...
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Table of Contents 13.2.12 Register Definition of RTC module . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 14 High-Speed Synchronous ...
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... Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 24.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 24.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 24.4 USB Full-speed (12 Mbit/s) Driver Characteristics . . . . . . . . . . . . . . . . . . 444 24.5 Failsafe operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 24.6 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 24.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 24.7.1 Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 24.7.2 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 24.7.3 External Clock Drive XTAL1 ...
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Table of Contents 24.8.1.1 AC Characteristics, Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . .451 24.8.1.2 AC Characteristics, Demultiplexed Bus . . ...
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Embedded C166 with USB, USART and SSC C161U Version 1.3 1 Overview C161U is a new low cost member of the Infineon Communication Controller family using low power CMOS technology. The successful Infineon C166 16-bit full-static core with a full-speed ...
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Peripheral Event Controller (PEC) for 8 independent DMA channels – 16 Dynamically Programmable Priority-Level Interrupt System – Two External Interrupts – SW-configurative Input/Output (I/O) Ports, some with Interrupt Capabilities – 8-bit or 16-bit External Data Bus ...
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Power Management Besides the basic power-save (power-reduction) modes Idle mode and Power down mode, the C161U offers a number of additional power management features, which can be selectively used for effective power reduction. Refer to Table 1. Table 1 Overview ...
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Logic Symbol C161U logic symbol is shown in Figure 1 below. Full Speed USB SSC/SCI Figure 1 C161U Logic Symbol Data Sheet P-TQFP-100 C161U Clock 14 C161U Overview Address/Data Bus General Purpose I/O USART 2001-04-19 ...
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... VDD P6.5 90 P6.6 P6.7 VSSU DMNS DPLS 95 VDD P2.0 P2.1 TEST TRST 100 1 5 Figure 2 Pinning Diagram of the C161U Data Sheet 65 60 C161U SAF C161U - LF P-TQFP-100 C161U Overview 55 51 P0H.1 50 P0H.0 P0L.7 P0L.6 P0L.5 P0L.4 45 VDD VSS P0L.3 P0L.2 P0L.1 40 P0L.0 ...
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Typical Applications 1.4.1 Personal Computer (PC) Peripherals Applications V.24-Interface USB Host Interface Figure 3 C161U in Personal Computer Peripherals Data Sheet CD-ROM Player AUDIO Device Multimedia Keyboard Joystick SRAM Flash 16 C161U Overview C161U C166 Core XBUS EBC RAM ...
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Pin Descriptions 2.1 C161U Pin Diagram Fast EXnINT(1:0) External or I/O Interrupts GPT1/2 Port I/O or MRST SSC/SCI I/O or MTSR Serial Port I/O or SCLK I/O or TxD USART/ASC Port I/O or RxD OCDS USB Port Figure 4 ...
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C161U Pin Definitions and Functions Table 2 Microprocessor Bus and Control Signals Pin No. Symbol PORT0: 39-42, 45-48, P0L0- 49-50, 53-58 P0L7, P0H0- P0H7 PORT1: 61-68, 71-78 P1L0- P1L7, P1H0- P1H7 Data Sheet Input (I) Function Output (O) I/O ...
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Table 2 Microprocessor Bus and Control Signals (cont’d) Pin No. Symbol 23, 26-29 P4.0 - P4.4 81 RSTIN 82 RSTOUT O 83 NMI Data Sheet Input (I) Function Output (O) I/O PORT4 is an 5-bit bidirectional I/O port ...
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Table 2 Microprocessor Bus and Control Signals (cont’d) Pin No. Symbol 84-87, 90-92 P6.0- P6.3, P6.5- P6.7 97-98 P2.0- P2 WR/WRL O 37 ALE Data Sheet Input (I) Function Output (O) O Port6 is an 7-bit bidirectional ...
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Table 2 Microprocessor Bus and Control Signals (cont’d) Pin No. Symbol 36 READY 38 EA Data Sheet Input (I) Function Output (O) I Ready Input. When the ready function is enabled, a high level at this pin during an external ...
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Table 3 General Purpose I/O and Control Signals Pin No. Symbol 10-12, 16-22 P3.3, P3.5- P3.6, P3.8- P3.13, P3.15 Data Sheet Input (I) Function Output (O) I/O PORT3 is a 10-bit bidirectional I/O port I/O bit-wise programmable for ...
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Table 4 USB Interface Signals Pin No. Symbol 95 DPLS 94 DMNS Table 5 Clock Interface Signals Pin No. Symbol 7 XTAL1 8 XTAL2 13 CLKMODE I Table 6 Boundary Scan / JTAG / Test Interface Signals/OCDS Pin No. Symbol ...
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Table 6 Boundary Scan / JTAG / Test Interface Signals/OCDS Pin No. Symbol 3 TDO 4 TMS 100 TRST 99 TEST 31 BRKIN 30 BRKOUT O Data Sheet Input (I) Function Output (O) O Boundary Scan Test Data Output. During ...
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Table 7 Power/Ground Signals Pin No. Symbol 15, 25, 33, 44, VDD 52, 60, 70, 80, 89 14, 24, 32, VSS 43, 51, 59, 69, 79 VDDAX 6 VSSAX 93 VSSU Data Sheet Input (I) Function ...
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Architectural Overview The architecture of the C161U combines the advantages of both RISC and CISC processors in a very well-balanced way. The sum of the features which are combined result in a high performance microcontroller, which is the right ...
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Basic CPU Concepts and Optimizations The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware is provided for a separate multiply and divide unit, a ...
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High Instruction Bandwidth / Fast Execution Based on the hardware provisions, most of the C161U's instructions can be executed in just one machine cycle, which requires 55 MHz CPU clock. For example, shift and rotate instructions are ...
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An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle. Thus, these operations use two coupled 16-bit registers, ...
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No special instructions are required to perform loops, and loops are automatically detected during execution of branch instructions. • The second loop enhancement allows the detection of the end of a table and avoids the use of two compare ...
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The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly functional C161U instruction set which includes the following instruction classes: • Arithmetic Instructions • Logical Instructions • Boolean Bit ...
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With an interrupt response time within a range from just 140 ns to 280 ns (in case of internal program execution), the C161U is capable of reacting very fast on non- deterministic events. Its fast external interrupt inputs are sampled ...
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On-Chip System Resources C161U controllers provide a number of powerful system resources designed around the CPU. The combination of CPU and these resources results in the high performance of the members of this controller family. Peripheral Event Controller (PEC) ...
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CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack 1024 words is ...
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... The on-chip PLL circuit allows operation of the C161U on a low frequency external clock while still providing maximum performance. The PLL generates a CPU clock signal with 50% duty cycle. The PLL also provides fail safe mechanisms which allow the detection of frequency deviations and the execution of emergency actions in case of an external clock failure ...
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All AC and DC specifications described in Chapter 24, "AC/DC Characteristics" must be fulfilled. 5. The input frequency of the internal oscillator circuit is 4 MHz MHz. This applies only external crystal is used. ...
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Note: All supported clock modes for the C161U are shown in Table 8. Because of the limited size of the register, there are not all combinations adjustable, which can be derived theoretical from . Table 8 C161U Clock Generation Modes ...
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When PLL operation is selected the CPU clock is a selectable multiple of the oscillator frequency, ie. the input frequency. The table above lists the possible selections. The PLL constantly synchronizes to the external clock signal. Due to the fact ...
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Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset. 3.4 On-Chip Peripheral Blocks C161U clearly separates peripherals from the core. This structure permits the maximum number of operations to be performed in ...
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Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock (f oscillator derives the CPU clock from the crystal or from the external clock signal. The clock signal which is gated to the peripherals is independent ...
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Parallel Ports C161U provides I/O lines which are organized into seven input/output ports. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are ...
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SSC supports full-duplex synchronous communication Mbaud @ 36 MHz CPU clock in SSC master mode and MBaud @ 36 MHz in SSC slave mode. It may be configured so it interfaces with serially ...
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... Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’ ...
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Protected Bits C161U provides a special mechanism to protect bits which can be modified by the on- chip hardware from being changed unintentionally by software accesses to related bits (see also chapter “The Central Processing Unit”). The following bits ...
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Memory Organization The memory space of the C161U is configured in a “Von Neumann” architecture. This means that code and data are accessed within the same linear address space. All of the physically separated memory areas, internal RAM, the ...
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Bytes are stored at even or odd byte addresses. Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte address. Double words (code ...
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Internal RAM and SFR Area RAM/SFR area is located within data page 3 and provides access to the internal RAM (IRAM, organized as X*16) and to two 512 Byte blocks of Special Function Registers (SFRs). C161U provides 3 KByte ...
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Note: The upper 256 Bytes of SFR area, ESFR area and internal RAM are bit- addressable (see shaded blocks in Figure 10). Code accesses are always made on even byte addresses. The highest possible code storage location in the internal ...
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The technique of implementing this circular stack is described in chapter “System Programming”. General Purpose Registers The General Purpose Registers (GPRs) use a block of 16 consecutive words within the internal RAM. The Context Pointer (CP) register determines the base ...
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Context Pointer register (CP) is active at a given time, however. Selecting a new active register bank is simply done by updating the CP register. A particular Switch Context (SCXT) instruction performs register bank switching and an automatic ...
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Whenever a PEC data transfer is performed, the pair of source and destination pointers, which is selected by the specified PEC channel number, is accessed independent of the current DPP register contents and also the locations referred to by these ...
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MOV T8REL order to minimize the use of the EXTR instructions the ESFR area mostly holds registers which are mainly required for initialization and mode selection. Registers that need to be accessed frequently are allocated to ...
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For PEC data transfers the external memory can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. The external memory is not provided for single bit storage and therefore it is not ...
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Central Processor Unit Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and to store the previously calculated ...
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The on-chip peripheral units of the C161U work nearly independent of the CPU with a separate clock generator. Data and control information is interchanged between the CPU and these peripherals via Special Function Registers (SFRs). Whenever peripherals need a non-deterministic ...
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Instruction Pipelining The instruction pipeline of the C161U partitiones instruction processing into four stages of which each one has its individual task: 1st –>FETCH In this stage the instruction selected by the Instruction Pointer (IP) and the Code Segment ...
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Instruction pipelining increases the average instruction throughput considered over a certain period of time. In the following, any execution time specification of an instruction always refers to the average execution time due to pipelined parallel instruction processing. 1 Machine Cycle ...
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If a conditional branch is not taken, there is no deviation from the sequential program flow, and thus no extra time is required. In this case the instruction after the branch instruction will enter the decode stage of the pipeline ...
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Particular Pipeline Effects Since up to four different instructions are processed simultaneously, additional hardware has been spent in the C161U to consider all causal dependencies which may exist on instructions in different pipeline stages without a loss of performance. This ...
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I : MOV SP, #0FA40H .... n POP R0 n+2 Note: Conflicts with instructions writing to the stack (PUSH, CALL, SCXT) are solved internally by the CPU logic. External Memory Access Sequences The effect described ...
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Initialization of Port Pins Modifications of the direction of port pins (input or output) become effective only after the instruction following the modifying instruction. As bit instructions (BSET, BCLR) use internal read-modify-write sequences accessing the whole port, instructions modifying the ...
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Bit-Handling and Bit-Protection C161U provides several mechanisms to manipulate bits. These mechanisms either manipulate software flags within the internal RAM, control on-chip peripherals via control bits in their respective SFRs or control I/O functions via port pins. The instructions ...
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Instruction State Times Basically, the time to execute an instruction depends on where the instruction is fetched from, and where possible operands are read from or written to. The fastest processing mode of the C161U is to execute a ...
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Table 9 Minimum Execution Times Memory Area Internal RAM 16-bit Demux Bus 16-bit Mux Bus 8-bit Demux Bus 8-bit Mux Bus Execution from the internal RAM provides flexibility in terms of loadable and modifyable code on the account of execution ...
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The PSW, SP, and MDC registers can be modified not only explicitly by the programmer, but also implicitly by the CPU during normal instruction processing. Note that any explicit write request (via software SFR supersedes a simultaneous modification ...
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SYSCON (FF12 / ROM SGT STKSZ S1 DIS Bit Function XPER- Reserved SHARE The XPER-SHARE mode, known from other C16x Infineon derivatives, is not supported in the C161U. ...
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Bit Function ROMEN Internal Boot-ROM Enable ’0’: Internal Boot-ROM is disabled. Access of the lower 32k address space will be linked to external memory. During normal operation, bit ROMEN must always be set to ’0’ signal ’1’: Internal Boot-ROM is ...
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IP are saved to and restored from the stack. After reset the segmented memory mode is selected. Note: Bit SGTDIS controls if the CSP register is pushed onto the system stack in addition to the IP register before ...
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PSW (FF10 / ILVL IEN rw rw Bit Function N Negative Result Set, when the result of an ALU operation is negative. C Carry Flag Set, when the result of an ...
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N-flag can be interpreted as the sign bit of the result (negative: N=’1’, positive: N=’0’). Negative numbers are always represented as the 2's complement of the corresponding positive number. The range of signed numbers extends from '–8000 to '+7FFF ...
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For Boolean bit operations with two operands the V-flag represents the logical ORing of the two specified bits. Table 10 Shift Right Rounding Error Evaluation C-Flag V-Flag • Z-Flag: The Z-flag is ...
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CPU Interrupt Status (IEN, ILVL) The Interrupt Enable bit allows to globally enable (IEN=’1’) or disable (IEN=’0’) interrupts. The four-bit Interrupt Level field (ILVL) specifies the priority of the current CPU activity. The interrupt level is updated by hardware upon ...
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CSP (FE08 / Bit Function SEGNR Segment Number Specifies the code segment, from where the current instruction fetched. ...
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Code Segment FF’FFFF H 255 254 FE’0000 H 1 01’0000 H 0 00’0000 H Figure 16 Addressing via the Code Segment Pointer Note: When segmentation is disabled, the IP value is used directly as the 16-bit address. Data Page Pointers ...
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DPP0 (FE00 / DPP1 (FE02 / ...
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In case of the segmented memory mode the selected number of segment address bits (via bitfield SALSEL) of the respective DPP register is output on the respective segment address pins of Port 4 for all external data accesses. A DPP ...
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CP (FE10 / Bit Function cp Modifiable portion of register CP Specifies the (word) base address of the current register bank. When writing ...
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Context Pointer Figure 18 Register Bank Selection via Register CP Several addressing modes use register CP implicitly for address calculations. The addressing modes mentioned below are described in chapter “Instruction Set Summary”. Short 4-Bit GPR Addresses (mnemonic Rb) ...
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Short 8-Bit Register Addresses (mnemonic: reg or bitoff) within a range from F0 FF interpret the four least significant bits as short 4-bit GPR address, while the four H most significant bits are ignored. The respective physical GPR address calculation ...
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SP (FE12 / Bit Function sp Modifiable portion of register SP Specifies the top of the internal system stack. Stack Overflow Pointer STKOV ...
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Then, six additional stack word locations are required to push IP, PSW, and CSP for both the interrupt service routine and the hardware trap service routine. More details about the stack overflow trap service routine and virtual stack management are ...
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This control mechanism is not triggered, ie. no stack trap is generated, when • the stack pointer SP is directly updated via MOV instructions • the limits of the stack area (STKOV, STKUN) are changed, so that SP is outside ...
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MDL (FE0E / Bit Function mdl Specifies the low order 16 bits of the 32-bit multiply and divide register MD. Whenever this register is updated via software, the Multiply/Divide Register In ...
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MDC (FF0E / Bit Function MDRIU Multiply/Divide Register In Use ‘0’: Cleared, when register MDL is read via software. ‘1’: Set ...
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ZEROS (FF1C / Constant Ones Register ONES All bits of this bit-addressable register are fixed to '1' by hardware. This register ...
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Extension of Source and Destination Pointers The source and destination pointers specify the locations between which the data moved. For each of the eight PEC channels the source and destination pointers are specified by one SFR ...
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Table 11 PEC Segment Number Register Addresses Register Address PECSN0 FED0 / 68 H PECSN1 FED2 / 69 H PECSN2 FED4 / 6A H PECSN3 FED6 / 6B H Data Sheet Reg. Space Register SFR PECSN4 H SFR PECSN5 H ...
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Extended PEC Channel Control The PEC control registers with the extended functionality and their application for new PEC control are defined as follows: PECCx (Addresses: see table CLT ...
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PEC Control Register Addresses Register Address PECC0 FEC0 / PECC1 FEC2 / PECC2 FEC4 / PECC3 FEC6 / Byte/Word Transfer bit BWT controls byte or a ...
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The PEC transfer counter allows to service a specified number of requests by the respective PEC channel, and then (when COUNT reaches 00 service routine, which is associated with the priority level. After each PEC transfer the COUNT field is ...
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In packet transfer mode, a COUNT2 value change from 0001 PEC channel and the CL flag is set in the respective PEC control register. In these cases the CPU is requested to update the PEC control and pointer registers ...
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PECXCx (FEFy / 7z , see table Bit Function COUNT2 Extended PEC Transfer Count Counts PEC transfers and influences the channel’s action in Packet transfer mode PEC Extended Control Register Addresses Register Address ...
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For each pair of linked channels, an internal channel flag, the Channel Link Toggle flag Table 12 PEC Channels which could be linked together Linked PEC Channels PEC Channel A channel 0 channel 2 channel 4 channel 6 CLT identifies ...
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DMA - External PEC (EPEC) EPEC provides fast and easy means to transfer single data between any memory location within the address space by using the XBUS. The advantages are reduced XBUS protocol handling and capability of addressing all ...
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The EPEC Block diagram is shown in Figure 20 below. Core EPEC PEC epec_ptr(23:0) XBUS Figure 20 DMA/EPEC Block Diagram The TX_REQn and RX_REQn shown in Figure 20 will be generated by the USBD to request a word transfer over ...
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EPEC Register Description The EPEC register description below shows the individual channel assignments between requesting USB source interrupts and each individual EPEC channel. The EPEC Register Base address is 00ED00 The detailed register description is shown below. Table 13 ...
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Table 13 EPEC Register Summary (cont’d) 00ED00 + Name H 38 EPEC_DPTR_OUT_R0 EPEC_DPTR_OUT_R0 EPEC_DPTR_REG10 H 3E EPEC_DPTR_REG11 H 40 EPEC_DPTR_REG20 H 42 EPEC_DPTR_REG21 H 44 EPEC_DPTR_REG30 H 46 EPEC_DPTR_REG31 H 48 EPEC_DPTR_REG40 H 4A ...
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Table 13 EPEC Register Summary (cont’d) 00ED00 + Name H 60 EPEC_CTRL_REG3 H 62 EPEC_CTRL_REG4 H 64 EPEC_CTRL_REG5 H 66 EPEC_CTRL_REG6 H 68 EPEC_CTRL_REG7 H 6A EPEC_INT_REG H 6C EPEC_INTMSK_REG H 6E..FF H Data Sheet DMA - External PEC (EPEC) ...
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EPEC Clock Control Register Address: ED00 H Name: EPECCLC Reserved Field Bits EPECEX_DIS 3 EPECGPSEN 2 EPECDIS 1 EPECDISR 0 RESERVED 15:4 The register EPEC CLC is clocked with the bus clock to be ...
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For on chip debugging support (OCDS) an additional bit EPEC GPSEN is introduced to stop the peripheral clock for arbitrary lengths of time during debugging if this function is enabled. If debugging mode is active, the peripheral core rejects write ...
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The EPEC source pointer registers (x1) provide the most significant 8-bits of the 24-bit source pointer for USB endpoints. EPEC_DPTR_REGx0 (x=7..0) Table 16 EPEC_DPTR_REGx0 Destination Pointer Register Bit No. Name 15:0 DPTRx(15:0) The EPEC destination pointer registers (x0) provide the ...
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Table 18 EPEC_CTRL_REGx Source Pointer Register Bit No. Name 13:12 REQ_SRC 11 CNT_UP_DN 10 CLR 9:0 BYTE_CNT The EPEC Transmit Byte Length registers (x) provide the 10-bit Transmit bytes length of the actual packet to be send to the USB ...
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EPEC_INTMSK_REG Table 20 EPEC_INTMSK_REG Interrupt Register Bit No. Name 15:8 RxTxSTARTMSK 7:0 TXDONE_INTMSKx (x=7..0) The EPEC interrupt mask register masks out the end of an TX-packet transfer interrupt for an USB endpoint. 6.4 EPEC Transfer Example The EPEC (external peripheral ...
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After the interrupt generation unit has generated the interrupt pulse it waits for a write to the interrupt register. It then is ready to generate the next interrupt pulse to the CPU write to the interrupt register ...
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Interrupt and Trap Functions The architecture of the C161U supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. These mechanisms include: Normal Interrupt Processing ...
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Interrupt System Structure C161U provides separate interrupt nodes that may be assigned to 16 priority levels. The 4 lowest nodes are reserved for the CPU - thus nodes are available for all interrupts. ...
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Table 21 C161U Interrupts and PEC Service Requests Nr. Source of Interrupt or PEC Service Request irq(0) GPT Timer 2 irq(1) GPT Timer 3 irq(2) GPT Timer 4 irq(3) GPT Timer 5 irq(4) GPT Timer 6 irq(5) GPT CAPREL Register ...
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Nr. Source of Interrupt or PEC Service Request irq(26) UDC TX Done5 irq(27) UDC TX Done4 irq(28) UDC TX Done3 irq(29) UDC TX Done2 irq(30) UDC TX Done1 irq(31) UDC TX Done0 irq(32) UDC RX Done7 irq(33) UDC RX Done6 ...
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Note: The X-Bus interrupts xb(0) and xb(1), known from C16x device’s, are connected to the main interrupt node of the respective X-Bus peripheral: UTXRINT (xb(0) and irq(22)) and EPECINT (xb(1) and irq(40). Note: Each entry of the interrupt vector table ...
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Exception Condition Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction Normal Interrupt Processing and PEC Service During each instruction cycle one out of ...
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Interrupt Control Registers All interrupt control registers are organized identically. The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source, which is required during one round of prioritization, the upper ...
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This allows a normal CPU interrupt to respond to a completed PEC block transfer. Note: Modifying the Interrupt Request flag via software causes the same effects had been set or cleared by hardware. Interrupt ...
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Interrupt Control Register PEC Control Figure 21 Priority Levels and PEC Channels Simultaneous requests for PEC channels are prioritized according to the PEC channel number, where channel 0 has lowest and channel 7 has highest priority. Note: All sources that ...
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Note: All requests on levels 13...1 cannot initiate PEC transfers. They are always serviced by an interrupt service routine. No PECC register is associated and no COUNT field is checked. Interrupt Control Functions in the PSW The Processor Status Word ...
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Any request on the same or a lower level will not be acknowledged. The current CPU priority level may be adjusted via software to control which interrupt request sources will ...
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COUNT may allow a specified number of PEC transfers, unlimited transfers or no PEC service at all. The table below summarizes, how the COUNT field itself, the interrupt requests flag IR and the PEC channel action depends on the ...
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Source and destination pointers specifiy the locations between which the data moved. A pair of pointers (SRCPx and DSTPx) is associated with each of the 8 PEC channels. These pointers do not reside in specific SFRs, but ...
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Prioritization of Interrupt and PEC Service Requests Interrupt and PEC service requests from all sources can be enabled, so they are arbitrated and serviced (if they win), or they may be disabled, so their requests are disregarded and not ...
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The 19 interrupt sources (excluding PEC requests) are so assigned to 3 classes of priority rather than to 7 different levels, as the hardware support would do. Table 24 Software controlled Interrupt Classes (Example) ILVL GLVL (Priority ...
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Saving the Status during Interrupt Service Before an interrupt request that has been arbitrated is actually serviced, the status of the current task is automatically saved on the system stack. The CPU status (PSW) is saved along with the ...
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When the interrupt service routine is left (RETI is executed), the status information is popped from the system stack in the reverse order, taking into account the value of bit SGTDIS. Context Switching An interrupt service routine usually saves all ...
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Interrupt Response Times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction (I1) being fetched from the interrupt vector location. The basic interrupt response time ...
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When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, or instruction N explicitly writes to the PSW or the SP, the minimum interrupt response time may be extended by 1 state time for each of these conditions. ...
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RAM. Note: A bus access in this context includes all delays which can occur ...
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The PEC response time is increased by all delays of the instructions in the pipeline that are executed before starting the data transfer (including N). • When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, the minimum PEC ...
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External Interrupts Although the C161U has no dedicated INTR input pins, it provides many possibilities to react on external asynchronous events by using a number of I/O lines for interrupt input. The interrupt function may either be combined with ...
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Note: The non-maskable interrupt input pin NMI and the reset input RSTIN provide another possibility for the CPU to react on an external input signal. NMI and RSTIN are dedicated input pins, which cause hardware traps. 7.8.1 Fast External Interrupts ...
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External Interrupt Source Control Fast external interrupts may also have interrupt sources selected from other peripherals. This function is very advantageous in Slow Down mode or in Sleep mode, if for example the SSC interface shall be used to ...
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Bit Function EXI6SS 0 0: Must be set to ’00’ Not allowed Not allowed Not allowed. EXI7SS 0 0: Not allowed Input from source RTC_INT Not allowed Not ...
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ISNC register is defined as follows: ISNC (F1DE / Bit Function T14IR T14 Overflow Interrupt Request Flag ‘0’: No request pending ‘1’: This source has raised an interrupt request T14IE T14 ...
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FEIxIC (See Table Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields. Table 26 Fast External Interrupt Control Register Addresses Register FEI0IC ...
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Hardware Traps Hardware traps are issued by faults or specific system states that occur during runtime of a program (not identified at assembly time). A ...
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TFR (FFAC / STK STK NMI - - Bit Function ILLBUS Illegal External Bus Access Flag An external access has been attempted with no ...
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B traps is determined by software in the trap service routine. A class A trap occurring during the execution of a class B trap service routine will be serviced immediately. During the execution of a ...
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IP value represents the address of the instruction after the instruction following the add instruction. Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid C161U opcode, the UNDOPC flag ...
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Parallel Ports In order to accept or generate single external control signals or parallel data, the C161U provides parallel I/O lines. C161U features Port 0 (inculdes 8 bit P0H and 8 bit P0L), Port 1 (8 ...
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Data Input / Output Registers P0L P0H P1L P1H Figure 27 SFRs and Pins associated with the Parallel Ports In the C161U certain ports provide Open Drain Control, which allows to switch the output driver of ...
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Q Push/Pull Output Driver Figure 28 Output Drivers in Push/Pull Mode and in Open Drain Mode Alternate Port Functions Each port line has one programmable alternate input or output function associated. PORT0 and PORT1 may be used as the address ...
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This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch. On most of the port lines, the user software is responsible for setting the proper ...
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PORT0 The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0, respectively. Both halfs of PORT0 can be written (eg. via a PEC transfer) without effecting the other half. If this port is used ...
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P0L (FF00 / P0H (FF02 / Bit Function P0X.y Port data register ...
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ODP0H (FE22 / Bit Function ODP0H.y Port0H Open Drain control register bit y ODP0H Port line P0H.y output driver in push/pull mode ODP0H.y = ...
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P0LPUDEN (FE64 / P0HPUDEN (FE66 / Bit Function P0xPUDEN.y Pulldown/Pullup Enable 0: ...
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Alternate Functions of PORT0 When an external bus is enabled, PORT0 is used as data bus or address/data bus. Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for I/O (provided that no other ...
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Alternate Function P0H.7 P0H.6 P0H.5 P0H.4 P0H P0H.3 P0H.2 P0H.1 P0H.0 PORT0 P0L.7 P0L.6 P0L.5 P0L.4 P0L P0L.3 P0L.2 P0L.1 P0L.0 General Purpose Input/Output Figure 29 PORT0 I/O and Alternate Functions When an external bus mode is enabled, the direction ...
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Write DP0H.y/DP0L.y Direction Latch Read DP0H.y/DP0L Write P0H.y/P0L Port Output Latch Read P0H.y/P0L 7...0 Figure 30 Block Diagram of a PORT0 Pin Data Sheet Alternate 1 Direction MUX ...
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PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halfs of PORT1 can be written (eg. via a PEC transfer) without effecting the other half. If this port is used ...
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P1L (FF04 / P1H (FF06 / Bit Function P1X.y Port data register ...
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ODP1H (FE26 / Bit Function ODP1x.y Port1x Open Drain control register bit y ODP1x Port line P1x.y output driver in push/pull mode ODP1x.y = ...
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P1LPUDEN (FE70 / P1HPUDEN (FE72 / Bit Function P1xPUDEN.y Pulldown/Pullup Enable P1xPUDEN.y ...
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Alternate Functions of PORT1 When a demultiplexed external bus is enabled, PORT1 is used as address bus. Note that demultiplexed bus modes use PORT1 as a 16-bit port. Otherwise all 16 port lines can be used for general purpose ...
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Write DP1H.y/DP1L.y Direction Latch Read DP1H.y/DP1L Write P1H.y/P1L Port Output Latch Read P1H.y/P1L 7...0 Figure 32 Block Diagram of a PORT1 Pin 8.3 PORT2 In the C161U Port ...
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P2 (FFC0 / Bit Function P2.y Port data register P2 bit y DP2 (FFC2 / ...
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Bit Function P2PUDSEL.y Pulldown/Pullup Selection P2PUDSEL internal programmable pulldown transistor is selected P2PUDSEL internal programmable pullup transistor is selected P2PUDEN (FE7A / ...
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Alternate Function Port 2 General Purpose Input/Output Figure 33 Port 2 I/O and Alternate Functions The pins of Port 2 combine internal bus data and alternate data output before the port latch input. Note: As opposed to the C161U, in ...
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Write ODP2.y Open Drain Latch Read ODP2.y Write DP2 Direction e Latch r n Read DP2 Write P2.y s Port Output Latch Read P2.y Figure 34 Block Diagram of a Port 2 Pin ( ...
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PORT3 If this 10-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP3. Each port lines can be switched into push/pull or open drain mode via the ...
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P3 (FFC4 / P3.15 - P3.13 P3.12 P3. Bit Function P3.y Port data register P3 bit y DP3 (FFC6 / ...
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Bit Function P3PUDSEL.y Pulldown/Pullup Selection P3PUDSEL internal programmable pulldown transistor is selected P3PUDSEL internal programmable pullup transistor is selected P3PUDEN (FE80 / P3PU P3PU P3PU P3PU DEN. ...
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Table 28 Alternate Functions of Port 3 Port 3 Alternate Function Pin P3.0 --- P3.1 --- P3.2 --- P3.3 T3OUT P3.4 --- P3.5 T4IN P3.6 T3IN P3.7 --- P3.8 MRST P3.9 MTSR P3.10 TxD0 P3.11 RxD0 P3.12 BHE/WRH P3.13 SCLK ...
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The port structure of the Port 3 pins depends on their alternate function (see figures below). When the on-chip peripheral associated with a Port 3 pin is configured to use the alternate input function, it reads the input latch, which ...
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Write ODP3.y Open Drain Latch Read ODP3.y Write DP3 Direction e Latch r n Read DP3 Write P3.y s Port Output Latch Read P3 13, 11...5, 3 Figure 36 Block Diagram of ...
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Pin P3.12 (BHE/WRH) is one more pin with an alternate output function. However, its structure is slightly different (see figure below), because after reset the BHE or WRH function must be used depending on the system startup configuration. In these ...
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PORT4 If this 5-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP4. Each port line can be switched into push/pull or open drain mode via the ...
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DP4 (FFCA / Bit Function DP4.y Port direction register DP4 bit y DP4 Port line P4 input (high-impedance) DP4 Port ...
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P4PUDEN (FE86 / Bit Function P4PUDEN.y Pulldown/Pullup Enable P4PUDEN internal programmable pull transistor is disabled P4PUDEN internal programmable pull transistor is enabled ...
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Table 29 Alternate Functions of Port 4 Port 4 Std. Function Pin SALSEL=0164 KB P4.0 Gen. purpose I/O P4.1 Gen. purpose I/O P4.2 Gen. purpose I/O P4.3 Gen. purpose I/O P4.4 Gen. purpose I/O 396 Write DP4.y Direction Latch Read ...
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PORT6 If this 7-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP6. Each port line can be switched into push/pull or open drain mode via the ...
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P6 (FFCC / Bit Function P6.y Port data register P6 bit y DP6 (FFCE / ...
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Bit Function P6PUDSEL.y Pulldown/Pullup Selection P6PUDSEL internal programmable pulldown transistor is selected P6PUDSEL internal programmable pullup transistor is selected P6PUDEN (FE92 / ...
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Table 30 Alternate Functions of Port 6 Port 6 Altern. Function Pin CSSEL = 10 P6.0 Gen. purpose I/O P6.1 Gen. purpose I/O P6.2 Gen. purpose I/O P6.3 Gen. purpose I/O P6.5 HOLDExternal hold request input P6.6 HLDAHold acknowledge output ...
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With ODP6.x = ‘1’ (open drain output selected), the internal pullup device will not be active during Hold mode; external pullup devices must be used in this case. When entering Hold mode the CS lines are actively driven high for ...
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The bus arbitration signals HOLD, HLDA and BREQ are selected with bit HLDEN in register PSW. When the bus arbitration signals are enabled via HLDEN, also these pins are switched automatically to the appropriate direction. Note that the pin drivers ...
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Dedicated Pins Most of the input/output or control signals of the functional the C161U are realized as alternate functions of pins of the parallel ports. There is, however, a number of signals that use separate pins, including the USB ...
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External Read Strobe RD controls the output drivers of external memory or peripherals when the C161U reads data from these external devices. During reset and during Hold mode an internal pullup ensures an inactive (high) level on the RD output. ...
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Figure 42 External Oscillator Circuitry Clock Mode Select CLKMODE CLKMODE must be LOW if an external crystal is used. HIGH signal enables the direct clock input path and switches the internal oscillator in power down mode.. Reset Input RSTIN allows ...
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External Bus Interface Although the C161U provides a powerful set of on-chip peripherals and on-chip RAM areas, these internal units only cover a small fraction of its address space MByte. The external bus interface allows ...
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Single Chip Mode Single chip mode is entered, when pin EA is high during reset. In this case register BUSCON0 is initialized with 0000 is enabled. In single chip mode the C161U operates only with and out of internal resources. ...
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Multiplexed Bus Modes In the multiplexed bus modes the 16-bit intra-segment address as well as the data use PORT0. The address is time-multiplexed with the data and has to be latched externally. The width of the required latch depends on ...
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Segment (P4) ALE BUS (P0) RD BUS (P0) WR Figure 44 Multiplexed Bus Cycle Demultiplexed Bus Modes In the demultiplexed bus modes the 16-bit intra-segment address is permanently output on PORT1, while the data uses PORT0 (16-bit data) or P0L ...
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Address (P1) Segment (P4) ALE BUS (P0) RD BUS (P0) WR Figure 45 Demultiplexed Bus Cycle Switching between the Bus Modes The EBC allows to switch between different bus modes dynamically, ie. subsequent external bus cycles may be executed in ...
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Note: Never change the configuration for an address area that currently supplies the instruction stream. Due to the internal pipelining it is very difficult to determine the first instruction fetch that will use the new configuration. Only change the configuration ...
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Demultiplexed Bus Cycle Address (P1) Address Segment (P4) ALE BUS (P0) RD BUS (P0) WR Figure 46 Switching from Demultiplexed to Multiplexed Bus Mode External Data Bus Width EBC can operate on 8-bit or 16-bit wide external memory/peripherals. A 16-bit ...
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Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE. The respective byte will be written on both data bus halfs. When reading bytes from an external 16-bit device, whole words may be read and ...
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SALSEL Segment Address Lines 1 1 Two: A17...A16 1 0 Seven: A20...A16 0 1 None 0 0 Four: A19...A16 CS Signal Generation During external accesses the EBC can generate a (programmable) number of CS lines on Port 6, which allow ...
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CSWEN CSREN Chip Select Mode Write Chip Select 1 1 Read/Write Chip Select Address Chip Select signals remain active until an access to another address window. An address chip select becomes active with the falling edge ...
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Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user programmable to allow to adapt wide range of different external bus and memory configurations with different types of memories and/or peripherals. ...
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ALE ADDR RD/WR DATA ALE ADDR RD/WR DATA ALECTL Figure 47 Programmable External Bus Cycle ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bits in ...
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Normal Multiplexed Bus Cycle Segment Address (P4) ALE BUS (P0) Address RD Address BUS (P0) WR Figure 48 ALE Length Control Programmable Memory Cycle Time C161U allows the user to adjust the controller's external bus cycles to the access time ...
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Segment ALE BUS (P0) Address RD BUS (P0) Address WR Figure 49 Memory Cycle Time The external bus cycles of the C161U can be extended for a memory or peripheral, which cannot keep pace with the controller’s maximum speed, by ...
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Segment ALE BUS (P0) Address RD Figure 50 Memory Tri-State Time The output of the next address on the external bus can be delayed for a memory or peripheral, which needs more time to switch off its bus drivers, by ...
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Segment ALE BUS (P0) RD BUS (P0 The Data drivers from the previous bus cycle should be disabled when the RD signal becomes active. Figure 51 Read/Write Delay The read/write delay is controlled via the RWDCx bits in ...
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Early WR deactivation is controlled via the EWENx bits in the BUSCON registers (see page 196). The WR signal will be shortened if bit EWENx is set to ’1’ signal. Default after reset is a standard WR signal (EWENx = ...
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... READY after the first sample point of the C161U, the controller samples an active READY and terminates the current bus cycle, which, of course, is too early. By inserting predefined waitstates the first READY sample point can be shifted to a time, where the peripheral has safely controlled the READY line (eg. after 2 waitstates in the figure above). Data Sheet ...
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Controlling the External Bus Controller A set of registers controls the functions of the EBC. General features like the usage of interface pins (WR, BHE), segmentation are controlled via register SYSCON. Note: For SYSCON register description, refer to page ...
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BUSCON0 (FF0C / CSW CSR RDY - - EN0 EN0 EN0 BUSCON1 (FF14 / CSW CSR ...
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Bit Function MTTCx Memory Tristate Time Control ‘0’: 1 waitstate ‘1’: No waitstate EWENx Early Write Enable Bit ‘0’: Normal write ‘1’: Early write is enabled. The write signal turns off one TCL earlier. In order to have no overlapping ...
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Bus Access Control CPU accesses to internal and external busses, e.g. to internal or external memories or peripherals, are controlled with the respective address ranges. These address ranges are supported by ’chip select’ functions for XBUS resources or for external ...
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ADDRSEL1 (FE18 / ADDRSEL2 (FE1A / ADDRSEL3(FE1C / ADDRSEL4 (FE1E / 0F ) ...
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For a given window size only those upper address bits of the start address are ...