SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 328

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
USB Interface Controller
The following handshake/status stage will be generated by the UDC core itself. The
application interface has to check for the zero length data IN/OUT token in reverse
direction of the actual transfer sent by the host at the end of the data stage. I.e. the
control read (IN token) will be terminated by an OUT token with zero length data transfer
and the control write by an IN token.
The status stage will be NACK’d by the device until the SW has processed the request.
A STALL will indicate to the host that the request cannot be completed successfully by
the device.
Isochronous, Bulk and Interrupt Endpoints
All these types of transfers are handled by the FIFO/EPEC mechanism described for IN
and OUT transactions above.
Standard Device Requests
Most of the standard device requests will be handled by the UDC internally, including
SETUP stage, optional DATA stage and STATUS stage. Only GET_DESCRIPTOR,
SET_DESCRIPTOR, SYNC_FRAME will be forwarded to the application bus and
handled by SW.
The 8-byte SETUP request will be captured in the SETUP registers. IN/OUT transactions
from the host will be NACK’d until the SW is ready. The SETUP registers cannot be
overwritten by the host until all 4 registers have been read.
The USB specification allows an early termination of control transfers. For control
requests with data transmission from device to host, this means that host can send a
status out packet even thought it had requested more bytes than actually were sent
during this transfer. If Software has already set up the next packet in the FIFO’s, this data
must not be transfered with the next control in request. The data can be flushed by
Software after receiving the empty status out packet or automatically this can be done
by setting the Auto Flash Enable of the CMD register.
Requests to device, interface or endpoints with no DATA stage have to be successfully
completed (incl. STATUS stage) within 2 ms. Requests with DATA stage require the first
data packet within 10 ms and all subsequent packets within 5 ms. The STATUS stage
must then be completed within 2 ms.
The UDC performs a zero data transfer write/read transaction on the application bus.
The application itself, i.e. USBD control has to identify this STATUS stage of the Control
Read/Write by a change of read/write direction and has to respond to this transaction by
proper handshake.
Data Sheet
328
2001-04-19