SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 209

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
When two C161Us are to be connected in this way the external glue logic can be left out.
In this case one of the controllers must be operated in its Master Mode (default after
reset, DP6.7=’0’) while the other one must be operated in its Slave Mode (selected with
DP6.7=’1’).
In Slave Mode the C161U inverts the direction of its HLDA pin and uses it as an input,
while the master’s HLDA pin remains an output. This approach does not require any
additional glue logic for the bus arbitration (see figure below).
Figure 54
When the bus arbitration is enabled (HLDEN=’1’) the three corresponding pins are
automatically controlled by the EBC. Normally the respective port direction register bits
retain their reset value which is ’0’. This selects Master Mode where the device operates
compatible with earlier versions. Slave Mode is enabled by intentionally switching pin
BREQ to output (DP6.7=’1’) which is neither required for Master Mode nor for earlier
devices.
Entering the Hold State
Access to the C161U’s external bus is requested by driving its HOLD input low. After
synchronizing this signal the C161U will complete a current external bus cycle (if any is
active), release the external bus and grant access to it by driving the HLDA output low.
During hold state the C161U treats the external bus interface as follows:
• Address and data bus(es) float to tri-state
• ALE is pulled low by an internal pulldown device
• Command lines are pulled high by internal pullup devices (RD, WR/WRL, BHE/WRH)
• CSx outputs are pulled high (push/pull mode) or float to tri-state (open drain mode)
Data Sheet
Sharing External Resources using Slave Mode
HOLD
HLDA
BREQ
209
BREQ
HOLD
HLDA
External Bus Interface
2001-04-19
C161U

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