SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 186

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Address Chip Select signals remain active until an access to another address window.
An address chip select becomes active with the falling edge of ALE and becomes
inactive with the falling edge of ALE of an external bus cycle that accesses a different
address area. No spikes will be generated on the chip select lines.
Read or Write Chip Select signals remain active only as long as the associated control
signal (RD or WR) is active. This also includes the programmable read/write delay. Read
chip select is only activated for read cycles, write chip select is only activated for write
cycles, read/write chip select is activated for both read and write cycles (write cycles are
assumed, if any of the signals WRH or WRL gets active). These modes save external
glue logic, when accessing external devices like latches or drivers that only provide a
single enable input.
Note: CS0 provides an address chip select directly after reset (except for single chip
Internal pullup devices hold all CS lines high during reset. After the end of a reset
sequence the pullup devices are switched off and the pin drivers control the pin levels
on the selected CS lines. Not selected CS lines will enter the high-impedance state and
are available for general purpose I/O.
The pullup devices are also active during bus hold on the selected CS lines, while HLDA
is active and the respective pin is switched to push/pull mode. Open drain outputs will
float during bus hold. In this case external pullup devices are required or the new bus
master is responsible for driving appropriate levels on the CS lines.
Segment Address versus Chip Select
The external bus interface of the C161U supports many configurations for the external
memory. By increasing the number of segment address lines the C161U can address a
linear address space of 256 KByte, 1 MByte or 2 MByte. This allows to implement a large
sequential memory area, and also allows to access a great number of external devices,
using an external decoder. By increasing the number of CS lines the C161U can access
memory banks or peripherals without external glue logic. These two features may be
combined to optimize the overall system performance. Enabling 4 segment address lines
and 4 chip select lines eg. allows to access four memory banks of 2 MByte each. So the
available address space is 8 MByte (without glue logic).
Note: Bit SGTDIS of register SYSCON defines, if the CSP register is saved during
CSWEN
x
1
1
mode) when the first instruction is fetched.
interrupt entry (segmentation active) or not (segmentation disabled).
CSREN
x
0
1
Chip Select Mode
Write Chip Select
Read/Write Chip Select
186
External Bus Interface
2001-04-19
C161U