SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 175

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

External Read Strobe RD controls the output drivers of external memory or peripherals
when the C161U reads data from these external devices. During reset and during Hold
mode an internal pullup ensures an inactive (high) level on the RD output.
External Write Strobe WR/WRL controls the data transfer from the C161U to an
external memory or peripheral device. This pin may either provide an general WR signal
activated for both byte and word write accesses, or specifically control the low byte of an
external 16-bit device (WRL) together with the signal WRH (alternate function of P3.12/
BHE). During reset and during Hold mode an internal pullup ensures an inactive (high)
level on the WR/WRL output.
Note: Whether RD and WR/WRL remain idle during X-peripheral accesses depends on
Ready Input READY receives a control signal from an external memory or peripheral
device that is used to terminate an external bus cycle, provided that this function is
enabled for the current bus cycle. READY may be used as synchronous READY or may
be evaluated asynchronously. When waitstates are defined for a READY controlled
address window the READY input is not evaluated during these waitstates.
External Access Enable Pin EA is dedicated for on-chip ROM derivates. In this case it
determines, if the chip after reset starts fetching code from the internal ROM area
(EA=’1’) or via the external bus interface (EA=’0’). For the ROM-less C161U be sure to
hold this input low.
Non-Maskable Interrupt Input NMI allows to trigger a high priority trap via an external
signal (eg. a power-fail signal). It also serves to validate the PWRDN instruction that
switches the C161U into Power-Down mode. The NMI pin is sampled with every CPU
clock cycle to detect transitions.
Oscillator Input XTAL1 and Output XTAL2 connect the internal Pierce oscillator to the
external crystal. The oscillator provides an inverter and a feedback element. The
standard external oscillator circuitry (see figure below) comprises the crystal, two low
end capacitors and series resistor to limit the current through the crystal. The additional
LC combination is only required for 3rd overtone crystals to suppress oscillation in the
fundamental mode. A test resistor (R
oscillation allowance of the oscillator circuitry.
An external clock signal may be fed to the input XTAL1, leaving XTAL2 open.
Note: It is strongly recommended to measure the oscillation allowance (or margin) in the
The following starting configuration is recommended to be used for the C161U:
Quarz: C
External: Circuitry: C
Note: Please check the Infineon Application Notes in addition to this recommendation.
Data Sheet
the value of bit VISIBLE of register SYSCON.
final target system (layout) to determine the optimum parameters for the oscillator
operation.
L
= 30 pF (max.), R
A
= C
B
= 47 pF (max.), no serial resistor (Rx2 = 0)
S
= 70 Ohm (max.), Accuracy: 96ppm or better
Q
) may be temporarily inserted to measure the
175
Dedicated Pins
2001-04-19
C161U