SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 220

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
Figure 60
If T3M = ‘010
line stops the timer. If T3M = ‘011
the timer. In addition, the timer can be turned on or off by software using bit T3R. The
timer will only run, if T3R = ‘1’ and the gate is active. It will stop, if either T3R = ‘0’ or the
gate is inactive.
Note: A transition of the gate signal at line T3IN does not cause an interrupt request.
Timer 3 in Counter Mode
Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON
to ‘001
T3IN, which is an alternate function of P3.6. The event causing an increment or
decrement of the timer can be a positive, a negative, or both a positive and a negative
transition at this line. Bit field T3I in control register T3CON selects the triggering
transition (see Table 37 below).
f
h w _ clk
T xIN
T xE U D
B
’. In counter mode timer T3 is clocked by a transition at the external input pin
2
T xI
n
B
: 1
Block Diagram of Core Timer T3 in Gated Timer Mode
T xU D
’, the timer is enabled when T3IN shows a low level. A high level at this
M U X
XO R
T xM
0
1
T xU D E
M U X
T xR
B
’, line T3IN must have a high level in order to enable
C ore T im e r T x
220
U p/
D ow n
T xO T L
General Purpose Timer Unit
T xO E
x=3
T xO U T
In te rrup t
R e qu es t
2001-04-19
M C B 02029
C161U

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