SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 315

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Port Control
SSC uses three pins of Port 3 to communicate with the external world. Pin P3.13/SCLK
serves as the clock line, while pins P3.8/MRST (Master Receive / Slave Transmit) and
P3.9/MTSR (Master Transmit / Slave Receive) serve as the serial data input/output lines.
The operation of these pins depends on the selected operating mode (master or slave).
In order to enable the alternate output functions of these pins instead of the general
purpose I/O operation, the respective port latches have to be set to '1', since the port
latch outputs and the alternate output lines are ANDed. When an alternate data output
line is not used (function disabled), it is held at a high level, allowing I/O operations via
the port latch. The direction of the port lines depends on the operating mode. The SSC
will automatically use the correct alternate input or output line of the ports when switching
modes. The direction of the pins, however, must be programmed by the user, as shown
in the tables. Using the open drain output feature helps to avoid bus contention problems
and reduces the need for hardwired hand-shaking or slave select lines. In this case it is
not always necessary to switch the direction of a port pin. The table below summarizes
the required values for the different modes and pins.
SSC Port Control
Note: In the table above, an 'x' means that the actual value is irrelevant in the respective
14.3
The serial channel SSC has its own dedicated 16-bit baud rate generator with 16-bit
reload capability, allowing baud rate generation independent from the timers.
The baud rate generator is clocked with the CPU clock divided by 2 (f
is counting downwards and can be started or stopped through the global enable bit
SSCEN in register SSCCON. Register SSCBR is the dual-function Baud Rate
Generator/Reload register. Reading SSCBR, while the SSC is enabled, returns the
Data Sheet
Pin
SCLK
MTSR
MRST
mode, however, it is recommended to set these bits to '1', so they are already in
the correct state when switching between master and slave mode.
Master Mode
Function
Serial Clock
Output
Serial Data
Output
Serial Data
Input
Baud Rate Generation
Port
Latch
P3.13 = ’1’ DP3.13=’1’ Serial Clock
P3.9 = ’1’
P3.8 = ’x’
Direction
DP3.9 = ’1’ Serial Data
DP3.8 = ’0’ Serial Data
315
High-Speed Synchronous Serial Interface
Slave Mode
Function
Input
Input
Output
Port
Latch
P3.13 = ’x’ DP3.13=’0
P3.9 = ’x’
P3.8 = ’1’
CPU
/2). The timer
Direction
’
DP3.9 = ’0’
DP3.8 = ’1’
2001-04-19
C161U