SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 132

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Hardware Traps
Hardware traps are issued by faults or specific system states that occur during runtime
of a program (not identified at assembly time). A hardware trap may also be triggered
intentionally, eg. to emulate additional instructions by generating an Illegal Opcode trap.
C161U distinguishes eight different hardware trap functions. When a hardware trap
condition has been detected, the CPU branches to the trap vector location for the
respective trap condition. Depending on the trap condition, the instruction which caused
the trap is either completed or cancelled (ie. it has no effect on the system state) before
the trap handling routine is entered.
Hardware traps are non-maskable and always have priority over every other CPU
activity. If several hardware trap conditions are detected within the same instruction
cycle, the highest priority trap is serviced (see table in section “Interrupt System
Structure”).
PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and
the CPU level in register PSW is set to the highest possible priority level (ie. level 15),
disabling all interrupts. The CSP is set to code segment zero, if segmentation is enabled.
A trap service routine must be terminated with the RETI instruction.
The eight hardware trap functions of the C161U are divided into two classes:
Class A traps are
• external Non-Maskable Interrupt (NMI)
• Stack Overflow
• Stack Underflow trap
These traps share the same trap priority, but have an individual vector address.
Class B traps are
• Undefined Opcode
• Protection Fault
• Illegal Word Operand Access
• llegal Instruction Access
• Illegal External Bus Access Trap
These traps share the same trap priority, and the same vector address.
The bit-addressable Trap Flag Register (TFR) allows a trap service routine to identify the
kind of trap which caused the exception. Each trap function is indicated by a separate
request flag. When a hardware trap occurs, the corresponding request flag in register
TFR is set to '1'.
by other traps or higher priority interrupts, other than when triggered by a
hardware trap.
132
Interrupt and Trap Functions
2001-04-19
C161U