SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 60

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
I
I
I
Note: Conflicts with instructions writing to the stack (PUSH, CALL, SCXT) are solved
The effect described here will only become noticeable, when watching the external
memory access sequences on the external bus (eg. by means of a Logic Analyzer).
Different pipeline stages can simultaneously put a request on the External Bus Controller
(EBC). The sequence of instructions processed by the CPU may diverge from the
sequence of the corresponding external memory accesses performed by the EBC, due
to the predefined priority of external memory accesses:
1st
2nd
3rd
Software modifications (implicit or explicit) of the PSW are done in the execute phase of
the respective instructions. In order to maintain fast interrupt responses, however, the
current interrupt prioritization round does not consider these changes, ie. an interrupt
request may be acknowledged after the instruction that disables interrupts via IEN or
ILVL or after the following instructions. Timecritical instruction sequences therefore
should not begin directly after the instruction disabling interrupts, as shown in the
following example:
INT_OFF:
CRIT_1ST:
CRIT_LAST:
INT_ON:
Note: The described delay of 1 instruction also applies for enabling the interrupts system
n
n+1
n+2
External Memory Access Sequences
Controlling Interrupts
: MOV SP, #0FA40H
: ....
: POP R0
internally by the CPU logic.
ie. no interrupt requests are acknowledged until the instruction following the
enabling instruction.
Write Data
Fetch Code
Read Data.
BCLR
I
I
. . .
I
BSET
N-1
N
N+x
IEN
IEN
; select a new top of stack
; must not be an instruction popping operands
; pop word value from new top of stack into R0
; from the system stack
; globally disable interrupts
; non-critical instruction
; begin of uninterruptable critical sequence
; end of uninterruptable critical sequence
; globally re-enable interrupts
60
Central Processor Unit
2001-04-19
C161U