SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 329

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
USB Interface Controller
Vendor/Class Requests
All Vendor/Class requests will be forwarded to the application bus and handled by SW.
The 8-byte SETUP request will be captured in the SETUP registers. IN/OUT transactions
from the host will be NACK’d until the SW is ready. The SETUP registers cannot be
overwritten by the host until all 4 registers have been read.
Requests to device, interface or endpoints with no DATA stage have to be successfully
completed (incl. STATUS stage) within 2 ms. Requests with DATA stage require the first
data packet within 10 ms and all subsequent packets within 5 ms. The STATUS stage
must then be completed within 2 ms.
The UDC performs a zero data transfer write/read transaction on the application bus.
The application itself, i.e. USBD control has to identify this STATUS stage of the Control
Read/Write by a change of read/write direction and has to respond to this transaction by
proper handshake.
Load Configuration Data
After power-up the UDC has to be loaded by the SW via control endpoint#0 Transmit
FIFO. The only buffers the UDC maintains will be the 17 EndPtBufs one for each physical
endpoint. The number of bytes written by the SW then equals 5x17, i.e. 85 bytes.
The first strobe will load the first byte into the MSB byte of EndPtBuf0(39:32) of
endpoint#0 and so on.
Latency Considerations
The latency time is considered to be the minimum/maximum accumulated time between
two EPEC transfers. Since the EPEC transfer is injected into the decode pipeline, the
latency time is determined by the previous commands which have already entered the
FETCH and DECODE stage of the pipeline.
USB data rate for a packet to be processed by the application is 12 Mbit/s. Since the
UDC samples 8 bits before the byte is transferred over the application bus, the FIFOs
are either read or written every 1.333 s to provide a full word access to/from the XBUS
interface. The first EPEC transfer at the start of a packet transfer over the XBUS, i.e. its
initial latency time, may be delayed by up to 4 * 1.333 s (i.e. 5.33 s) since each FIFO
is 8-byte deep.
Worst case: The worst case EPEC interrupt response time including external accesses
will occur, when instructions N and N+1 are executed out of external memory,
instructions N-1 and N require external operand read accesses and instructions N-3, N-
2 and N-1 write back external operands. In this case the EPEC response time is the time
to perform 7 word bus accesses.
with f
@24 MHz (TCL=21 ns) and 1 external waitstate:
CPU
= 7 * ext. bus accesses with 1 waitstate + 2 * states + 1 * ext. access for src/dest. pointer
Data Sheet
329
2001-04-19