SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 56

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
Central Processor Unit
5.1
Instruction Pipelining
The instruction pipeline of the C161U partitiones instruction processing into four stages
of which each one has its individual task:
1st –>FETCH
In this stage the instruction selected by the Instruction Pointer (IP) and the Code
Segment Pointer (CSP) is fetched from either the internal RAM, or external memory.
2nd –>DECODE
In this stage the instructions are decoded and, if required, the operand addresses are
calculated and the respective operands are fetched. For all instructions, which implicitly
access the system stack, the SP register is either decremented or incremented, as
specified. For branch instructions the Instruction Pointer and the Code Segment Pointer
are updated with the desired branch target address (provided that the branch is taken).
3rd –>EXECUTE
In this stage an operation is performed on the previously fetched operands in the ALU.
Additionally, the condition flags in the PSW register are updated as specified by the
instruction. All explicit writes to the SFR memory space and all auto-increment or auto-
decrement writes to GPRs used as indirect address pointers are performed during the
execute stage of an instruction, too.
4th –>WRITE BACK
In this stage all external operands and the remaining operands within the internal RAM
space are written back.
A particularity of the C161U are the so-called injected instructions. These injected
instructions are generated internally by the machine to provide the time needed to
process instructions, which cannot be processed within one machine cycle. They are
automatically injected into the decode stage of the pipeline, and then they pass through
the remaining stages like every standard instruction. Program interrupts are performed
by means of injected instructions, too. Although these internally injected instructions will
not be noticed in reality, they are introduced here to ease the explanation of the pipeline
in the following.
Sequential Instruction Processing
Each single instruction has to pass through each of the four pipeline stages regardless
of whether all possible stage operations are really performed or not. Since passing
through one pipeline stage takes at least one machine cycle, any isolated instruction
takes at least four machine cycles to be completed. Pipelining, however, allows parallel
(ie. simultaneous) processing of up to four instructions. Thus, most of the instructions
seem to be processed during one machine cycle as soon as the pipeline has been filled
once after reset (see figure below).
Data Sheet
56
2001-04-19