SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 46

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
Bytes are stored at even or odd byte addresses. Words are stored in ascending memory
locations with the low byte at an even byte address being followed by the high byte at
the next odd byte address. Double words (code only) are stored in ascending memory
locations as two subsequent words. Single bits are always stored in the specified bit
position at a word address. bit position 0 is the least significant bit of the byte at an even
byte address, and bit position 15 is the most significant bit of the byte at the next odd
byte address. bit addressing is supported for a part of the Special Function Registers, a
part of the internal RAM and for the General Purpose Registers.
Figure 9
Note: Byte units forming a single word or a double word must always be stored within
the same physical (internal, external, RAM) and organizational (page, segment)
memory area.
Storage of Words, Byte and Bits in a Byte Organized Memory
15
7
14
6
Word (High Byte)
Word (Low Byte)
Byte
Byte
Bits
Bits
46
MCD01996
8
0
xxxxF H
xxxx6
xxxx5 H
xxxx4 H
xxxx3 H
xxxx2 H
xxxx1 H
xxxx0 H
Memory Organization
H
2001-04-19
C161U

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