SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 310

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Figure 98
14.1
The different devices are connected through three lines. The definition of these lines is
always determined by the master: The line connected to the master's data output pin
MTSR is the transmit line, the receive line is connected to its data input line MRST, and
the clock line is connected to pin SCLK. Only the device selected for master operation
generates and outputs the serial clock on pin SCLK. All slaves receive this clock, so their
pin SCLK must be switched to input mode (DP3.13=’0’). The output of the master’s shift
register is connected to the external transmit line, which in turn is connected to the
slaves’ shift register input. The output of the slaves’ shift register is connected to the
external receive line in order to enable the master to receive the data shifted out of the
slave. The external connections are hard-wired, the function and direction of these pins
is determined by the master or slave operation of the individual device.
Note: The shift direction shown in the figure applies for MSB-first operation as well as for
When initializing the devices in this configuration, select one device for master operation
(SSCMS=’1’), all others must be programmed for slave operation (SSCMS=’0’).
Initialization includes the operating mode of the device's SSC and also the function of
the respective port lines (see “Port Control”).
SSCPO SSCPH
0
0
1
1
MTSR/MRST
LSB-first operation.
Pins
0
0
1
1
Full-Duplex Operation
Serial Clock Phase and Polarity Options
First
Bit
Shift Data
Latch Data
310
High-Speed Synchronous Serial Interface
Transmit Data
Serial Clock
SCLK
Last
Bit
2001-04-19
MCD01960
C161U